[U-Boot] [PATCH] mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flash

[Kumar Gala]

From: Lan Chunhe <b25806 at freescale.com>

Signed-off-by: Lan Chunhe <b25806 at freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang at freescale.com>
Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
 arch/ppc/cpu/mpc85xx/cpu_init.c |   15 +++++++++++++++
 arch/ppc/include/asm/fsl_lbc.h  |    6 +++++-
 2 files changed, 20 insertions(+), 1 deletions(-)

diff --git a/arch/ppc/cpu/mpc85xx/cpu_init.c b/arch/ppc/cpu/mpc85xx/cpu_init.c
index 9aea776..99431dc 100644
--- a/arch/ppc/cpu/mpc85xx/cpu_init.c
+++ b/arch/ppc/cpu/mpc85xx/cpu_init.c
@@ -262,6 +262,10 @@ void cpu_init_f (void)
 
 int cpu_init_r(void)
 {
+#ifdef CONFIG_SYS_LBC_LCRR
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+#endif
+
 	puts ("L2:    ");
 
 #if defined(CONFIG_L2_CACHE)
@@ -385,6 +389,17 @@ int cpu_init_r(void)
 #if defined(CONFIG_MP)
 	setup_mp();
 #endif
+
+#ifdef CONFIG_SYS_LBC_LCRR
+	/*
+	 * Modify the CLKDIV field of LCRR register to improve the writing
+	 * speed for NOR flash.
+	 */
+	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
+	__raw_readl(&lbc->lcrr);
+	isync();
+#endif
+
 	return 0;
 }
 
diff --git a/arch/ppc/include/asm/fsl_lbc.h b/arch/ppc/include/asm/fsl_lbc.h
index 5723de6..dfe8f79 100644
--- a/arch/ppc/include/asm/fsl_lbc.h
+++ b/arch/ppc/include/asm/fsl_lbc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008,2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -125,8 +125,12 @@
 #define OR_GPCM_SETA_SHIFT		3
 #define OR_GPCM_TRLX			0x00000004
 #define OR_GPCM_TRLX_SHIFT		2
+#define OR_GPCM_TRLX_CLEAR		0x00000000
+#define OR_GPCM_TRLX_SET		0x00000004
 #define OR_GPCM_EHTR			0x00000002
 #define OR_GPCM_EHTR_SHIFT		1
+#define OR_GPCM_EHTR_CLEAR		0x00000000
+#define OR_GPCM_EHTR_SET		0x00000002
 #define OR_GPCM_EAD			0x00000001
 #define OR_GPCM_EAD_SHIFT		0
 
-- 
1.6.0.6