[U-Boot] [PATCH 2/3] video: add support for display controller in MB86R0x SoCs

Matthias Weisser weisserm at arcor.de
Thu Apr 22 12:30:56 CEST 2010


This patch adds support for the display controller in
the MB86R0x SoCs.

Signed-off-by: Matthias Weisser <weisserm at arcor.de>
---
 drivers/video/Makefile      |    1 +
 drivers/video/cfb_console.c |    8 ++
 drivers/video/mb86r0xgdc.c  |  194 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 203 insertions(+), 0 deletions(-)
 create mode 100644 drivers/video/mb86r0xgdc.c

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index a5e339a..1a60ec6 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -32,6 +32,7 @@ COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
 COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
 COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o
+COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o
 COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_SED156X) += sed156x.o
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index d1f47c9..4769cdb 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -153,6 +153,14 @@ CONFIG_VIDEO_HW_CURSOR:	     - Uses the hardware cursor capability of the
 #endif
 
 /*****************************************************************************/
+/* Defines for the MB86R0xGDC driver					     */
+/*****************************************************************************/
+#ifdef CONFIG_VIDEO_MB86R0xGDC
+
+#define VIDEO_FB_16BPP_WORD_SWAP
+#endif
+
+/*****************************************************************************/
 /* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc	     */
 /*****************************************************************************/
 #include <video_fb.h>
diff --git a/drivers/video/mb86r0xgdc.c b/drivers/video/mb86r0xgdc.c
new file mode 100644
index 0000000..9022730
--- /dev/null
+++ b/drivers/video/mb86r0xgdc.c
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm at arcor.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mb86r0x.c - Graphic interface for Fujitsu MB86R0x integrated graphic
+ * controller. Derived from mb862xx.c
+ */
+
+#include <common.h>
+
+#include <malloc.h>
+#include <mb862xx.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <video_fb.h>
+#include "videomodes.h"
+
+/*
+ * 4MB (at the end of system RAM)
+ */
+#define VIDEO_MEM_SIZE		0x400000
+
+/*
+ * Graphic Device
+ */
+static GraphicDevice mb86r0x;
+
+void *video_hw_init(void)
+{
+	GraphicDevice *pGD = &mb86r0x;
+	struct ctfb_res_modes var_mode[2];
+	unsigned long *vid;
+	unsigned long div;
+	unsigned long dspBase[2];
+	char *penv;
+	int bpp;
+	int i, j;
+
+	memset(pGD, 0, sizeof(GraphicDevice));
+
+	dspBase[0] = MB86R0x_GDC_DISP0_PHYS_BASE;
+	dspBase[1] = MB86R0x_GDC_DISP1_PHYS_BASE;
+
+	pGD->frameAdrs = MB86R0x_GDC_PHYS_BASE;
+	pGD->gdfIndex = GDF_15BIT_555RGB;
+	pGD->gdfBytesPP = 2;
+
+	pGD->memSize = VIDEO_MEM_SIZE;
+	pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
+	vid = (unsigned long *)pGD->frameAdrs;
+
+	for (i = 0; i < 2; i++) {
+		char varName[32];
+		u32 dcm1, dcm2, dcm3;
+		u16 htp, hdp, hdb, hsp, vtr, vsp, vdp;
+		u8 hsw, vsw;
+		u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1;
+		u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh;
+
+		sprintf(varName, "gs_dsp_%d_param", i);
+
+		penv = getenv(varName);
+		if (penv == NULL) {
+			penv = getenv("videomode");
+			if ((i == 1) || (penv == NULL))
+				continue;
+		}
+
+		bpp = 0;
+		bpp = video_get_params(&var_mode[i], penv);
+
+		if (bpp == 0) {
+			var_mode[i].xres = 640;
+			var_mode[i].yres = 480;
+			var_mode[i].pixclock = 39721;	/* 25MHz */
+			var_mode[i].left_margin = 48;
+			var_mode[i].right_margin = 16;
+			var_mode[i].upper_margin = 33;
+			var_mode[i].lower_margin = 10;
+			var_mode[i].hsync_len = 96;
+			var_mode[i].vsync_len = 2;
+			var_mode[i].sync = 0;
+			var_mode[i].vmode = 0;
+		}
+
+		for (j = 0; j < var_mode[i].xres * var_mode[i].yres / 2; j++)
+			*vid++ = 0xFFFFFFFF;
+
+		pGD->winSizeX = var_mode[i].xres;
+		pGD->winSizeY = var_mode[i].yres;
+
+		/* LCD base clock is ~ 660MHZ. We do calculations in kHz */
+		div = 660000 / (1000000000L / var_mode[i].pixclock);
+		if (div > 64)
+			div = 64;
+		if (0 == div)
+			div = 1;
+
+		dcm1 = (div - 1) << 8;
+		dcm2 = 0x00000000;
+		dcm3 = 0x00000000;
+
+		htp = var_mode[i].left_margin + var_mode[i].xres +
+			var_mode[i].hsync_len + var_mode[i].right_margin;
+		hdp = var_mode[i].xres;
+		hdb = var_mode[i].xres;
+		hsp = var_mode[i].xres + var_mode[i].right_margin;
+		hsw = var_mode[i].hsync_len;
+
+		vsw = var_mode[i].vsync_len;
+		vtr = var_mode[i].upper_margin + var_mode[i].yres +
+			var_mode[i].vsync_len + var_mode[i].lower_margin;
+		vsp = var_mode[i].yres + var_mode[i].lower_margin;
+		vdp = var_mode[i].yres;
+
+		l2m =	((var_mode[i].yres - 1) << (0)) |
+			(((var_mode[i].xres * 2) / 64) << (16)) |
+			((1) << (31));
+
+		l2em = (1 << 0) | (1 << 1);
+
+		l2oa0 = pGD->frameAdrs;
+		l2da0 = pGD->frameAdrs;
+		l2oa1 = pGD->frameAdrs;
+		l2da1 = pGD->frameAdrs;
+		l2dx = 0;
+		l2dy = 0;
+		l2wx = 0;
+		l2wy = 0;
+		l2ww = var_mode[i].xres;
+		l2wh = var_mode[i].yres - 1;
+
+		writel(dcm1, dspBase[i] + GC_DCM1);
+		writel(dcm2, dspBase[i] + GC_DCM2);
+		writel(dcm3, dspBase[i] + GC_DCM3);
+
+		writew(htp, dspBase[i] + GC_HTP);
+		writew(hdp, dspBase[i] + GC_HDP);
+		writew(hdb, dspBase[i] + GC_HDB);
+		writew(hsp, dspBase[i] + GC_HSP);
+		writeb(hsw, dspBase[i] + GC_HSW);
+
+		writeb(vsw, dspBase[i] + GC_VSW);
+		writew(vtr, dspBase[i] + GC_VTR);
+		writew(vsp, dspBase[i] + GC_VSP);
+		writew(vdp, dspBase[i] + GC_VDP);
+
+		writel(l2m, dspBase[i] + GC_L2M);
+		writel(l2em, dspBase[i] + GC_L2EM);
+		writel(l2oa0, dspBase[i] + GC_L2OA0);
+		writel(l2da0, dspBase[i] + GC_L2DA0);
+		writel(l2oa1, dspBase[i] + GC_L2OA1);
+		writel(l2da1, dspBase[i] + GC_L2DA1);
+		writew(l2dx, dspBase[i] + GC_L2DX);
+		writew(l2dy, dspBase[i] + GC_L2DY);
+		writew(l2wx, dspBase[i] + GC_L2WX);
+		writew(l2wy, dspBase[i] + GC_L2WY);
+		writew(l2ww, dspBase[i] + GC_L2WW);
+		writew(l2wh, dspBase[i] + GC_L2WH);
+
+		writel(dcm1 | (1 << 18) | (1 << 31), dspBase[i] + GC_DCM1);
+	}
+
+	return pGD;
+}
+
+/*
+ * Set a RGB color in the LUT
+ */
+void video_set_lut(unsigned int index, unsigned char r,
+					unsigned char g, unsigned char b)
+{
+
+}
-- 
1.5.6.3



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