[U-Boot] [PATCH] p1022ds: fix switching of DIU/LBC signals

[Scott Wood]

On Wed, 01 Dec 2010 17:28:28 -0600
Timur Tabi <timur at freescale.com> wrote:

> Scott Wood wrote:
> >> You told me that since I'm doing a read following a write to uncached memory,
> >> > that I don't need a sync.
> > No, I was talking about a write followed by a read, to the same location.
> 
> That's what I said. Read following write == write followed by read.

Sorry, misread.

The sync I was concerned about wasn't between that write and the
following read, but between the read and whatever comes after the read.

> > out_8 should be fixed to behave like the other accessors.
> 
> Ok, but I'm not using any of the I/O accessors, so this doesn't affect me.

Yes you are, in set_mux_to_diu().  But it's actually setbits_8(), which
will do an in_8() first, which has synchronization, so it should be OK.

> I just need to make sure that the read is executed after the write, and that the
> read completes before I continue.

Right.  It was that last bit I was talking about.

> So I should I put an isync between the write and the read, 

Not necessary since they're the same address, and wouldn't help if they
weren't (you'd want sync or mbar 1 in that case, not isync).

> and a sync after the read?

If you were to immediately follow it with out_8 as currently defined,
yes.  But setbits_8 should be OK.

-Scott