[U-Boot] [PATCH v4 5/7] add Ben NanoNote board
Xiangfu Liu
xiangfu at openmobilefree.net
Wed Dec 8 07:20:47 CET 2010
Signed-off-by: Xiangfu Liu <xiangfu at openmobilefree.net>
---
board/xburst/nanonote/Makefile | 45 ++++++++
board/xburst/nanonote/config.mk | 31 ++++++
board/xburst/nanonote/nanonote.c | 96 +++++++++++++++++
board/xburst/nanonote/u-boot-nand.lds | 63 +++++++++++
include/configs/nanonote.h | 188 +++++++++++++++++++++++++++++++++
include/configs/qi_lb60.h | 28 +++++
6 files changed, 451 insertions(+), 0 deletions(-)
create mode 100644 board/xburst/nanonote/Makefile
create mode 100644 board/xburst/nanonote/config.mk
create mode 100644 board/xburst/nanonote/nanonote.c
create mode 100644 board/xburst/nanonote/u-boot-nand.lds
create mode 100644 include/configs/nanonote.h
create mode 100644 include/configs/qi_lb60.h
diff --git a/board/xburst/nanonote/Makefile b/board/xburst/nanonote/Makefile
new file mode 100644
index 0000000..2f5b4be
--- /dev/null
+++ b/board/xburst/nanonote/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor, <jlwei at ingenic.cn>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/xburst/nanonote/config.mk b/board/xburst/nanonote/config.mk
new file mode 100644
index 0000000..858e6a2
--- /dev/null
+++ b/board/xburst/nanonote/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006 Qi Hardware, Inc.
+# Author: Xiangfu Liu <xiangfu.z at gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x88000000
+
+# RAM version
+TEXT_BASE = 0x80100000
+endif
diff --git a/board/xburst/nanonote/nanonote.c b/board/xburst/nanonote/nanonote.c
new file mode 100644
index 0000000..1a577e0
--- /dev/null
+++ b/board/xburst/nanonote/nanonote.c
@@ -0,0 +1,96 @@
+/*
+ * Authors: Xiangfu Liu <xiangfu.z at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/jz4740.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_init(void)
+{
+ /* Initialize NAND Flash Pins */
+ __gpio_as_nand();
+
+ /* Initialize SDRAM pins */
+ __gpio_as_sdram_16bit_4720();
+
+ /* Initialize LCD pins */
+ __gpio_as_lcd_18bit();
+
+ /* Initialize MSC pins */
+ __gpio_as_msc();
+
+ /* Initialize Other pins */
+ unsigned int i;
+ for (i = 0; i < 7; i++){
+ __gpio_as_input(GPIO_KEYIN_BASE + i);
+ __gpio_enable_pull(GPIO_KEYIN_BASE + i);
+ }
+
+ for (i = 0; i < 8; i++) {
+ __gpio_as_output(GPIO_KEYOUT_BASE + i);
+ __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
+ }
+
+ __gpio_as_input(GPIO_KEYIN_8);
+ __gpio_enable_pull(GPIO_KEYIN_8);
+
+ /* enable the TP4, TP5 as UART0 */
+ __gpio_jtag_to_uart0();
+
+ __gpio_as_output(GPIO_AUDIO_POP);
+ __gpio_set_pin(GPIO_AUDIO_POP);
+
+ __gpio_as_output(GPIO_LCD_CS);
+ __gpio_clear_pin(GPIO_LCD_CS);
+
+ __gpio_as_output(GPIO_AMP_EN);
+ __gpio_clear_pin(GPIO_AMP_EN);
+
+ __gpio_as_output(GPIO_SDPW_EN);
+ __gpio_disable_pull(GPIO_SDPW_EN);
+ __gpio_clear_pin(GPIO_SDPW_EN);
+
+ __gpio_as_input(GPIO_SD_DETECT);
+ __gpio_disable_pull(GPIO_SD_DETECT);
+
+ __gpio_as_input(GPIO_USB_DETECT);
+ __gpio_enable_pull(GPIO_USB_DETECT);
+}
+
+static void cpm_init(void)
+{
+ __cpm_stop_ipu();
+ __cpm_stop_cim();
+ __cpm_stop_i2c();
+ __cpm_stop_ssi();
+ __cpm_stop_uart1();
+ __cpm_stop_sadc();
+ __cpm_stop_uhc();
+ __cpm_stop_udc();
+ __cpm_stop_aic1();
+}
+
+int board_early_init_f(void)
+{
+ gpio_init();
+ cpm_init();
+
+ return 0;
+}
+
+/* U-Boot common routines */
+int checkboard (void)
+{
+ printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %ld MHz)\n",
+ gd->cpu_clk / 1000000);
+
+ return 0;
+}
diff --git a/board/xburst/nanonote/u-boot-nand.lds b/board/xburst/nanonote/u-boot-nand.lds
new file mode 100644
index 0000000..a15a96e
--- /dev/null
+++ b/board/xburst/nanonote/u-boot-nand.lds
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei at ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .sdata : { *(.sdata) }
+
+ _gp = ALIGN(16);
+
+ __got_start = .;
+ .got : { *(.got) }
+ __got_end = .;
+
+ .sdata : { *(.sdata) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ uboot_end_data = .;
+ num_got_entries = (__got_end - __got_start) >> 2;
+
+ . = ALIGN(4);
+ .sbss : { *(.sbss) }
+ .bss : { *(.bss) }
+ uboot_end = .;
+}
diff --git a/include/configs/nanonote.h b/include/configs/nanonote.h
new file mode 100644
index 0000000..7425c25
--- /dev/null
+++ b/include/configs/nanonote.h
@@ -0,0 +1,188 @@
+/*
+ * Authors: Xiangfu Liu <xiangfu.z at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+/*
+ * This file contains the configuration parameters for the NanoNote.
+ */
+#ifndef __CONFIG_NANONOTE_H
+#define __CONFIG_NANONOTE_H
+
+#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
+#define CONFIG_JZSOC 1 /* Jz SoC */
+#define CONFIG_JZ4740 1 /* Jz4740 SoC */
+#define CONFIG_NAND_JZ4740
+#define CONFIG_NANONOTE
+
+#define BOOT_FROM_SDCARD 1
+#define BOOT_WITH_ENABLE_UART (1 << 1) /* Vaule for global_data.h gd->boot_option */
+
+#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
+#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
+#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
+#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
+
+#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
+#define CONFIG_BAUDRATE 57600
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SKIP_LOWLEVEL_INIT 1
+#define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_SYS_NO_FLASH 1
+#define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */
+#define CONFIG_ENV_OVERWRITE 1
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
+#define CONFIG_BOOTDELAY 0
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BOOTD /* bootd */
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_ECHO /* echo arguments */
+
+#define CONFIG_CMD_LOADB /* loadb */
+#define CONFIG_CMD_LOADS /* loads */
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
+#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SAVEENV /* saveenv */
+#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+#define CONFIG_CMD_SOURCE /* "source" command support */
+#define CONFIG_CMD_NAND
+
+/*
+ * Serial download configuration
+ */
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "NanoNote# " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
+
+#define CONFIG_SYS_MALLOC_LEN 896 * 1024
+#define CONFIG_SYS_BOOTPARAMS_LEN 128 * 1024
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x80800000
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
+
+/*
+ * NAND FLASH configuration
+ */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+
+/* NAND Boot config code */
+#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
+
+#define NANONOTE_NAND_SIZE 2 /* if board nand flash is 1GB, set to 1
+ * if board nand flash is 2GB, set to 2
+ * for change the PAGE_SIZE and BLOCK_SIZE
+ * will delete when there is no 1GB flash
+ */
+
+#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE)
+/* nand chip block size */
+#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10)
+/* nand bad block was marked at this page in a block, start from 0 */
+#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
+/* ECC offset position in oob area, default value is 6 if it isn't defined */
+#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 9
+
+#define CONFIG_SYS_NAND_BASE 0xB8000000
+#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
+
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 8k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ */
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+/* Start NUB from this addr*/
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
+
+#define CONFIG_ENV_SIZE (4 << 10)
+#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_SYS_NAND_BLOCK_SIZE)
+
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+/*
+ * SDRAM Info.
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+/*
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE 16384
+#define CONFIG_SYS_ICACHE_SIZE 16384
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+/*
+ * GPIO definition
+ */
+#define GPIO_LCD_CS (2 * 32 + 21)
+#define GPIO_AMP_EN (3 * 32 + 4)
+
+#define GPIO_SDPW_EN (3 * 32 + 2)
+#define GPIO_SD_DETECT (3 * 32 + 0)
+
+#define GPIO_BUZZ_PWM (3 * 32 + 27)
+#define GPIO_USB_DETECT (3 * 32 + 28)
+
+#define GPIO_AUDIO_POP (1 * 32 + 29)
+#define GPIO_COB_TEST (1 * 32 + 30)
+
+#define GPIO_KEYOUT_BASE (2 * 32 + 10)
+#define GPIO_KEYIN_BASE (3 * 32 + 18)
+#define GPIO_KEYIN_8 (3 * 32 + 26)
+
+#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
+#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
+
+#define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */
+#define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */
+#define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */
+#endif /* __CONFIG_NANONOTE_H */
diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
new file mode 100644
index 0000000..29ec805
--- /dev/null
+++ b/include/configs/qi_lb60.h
@@ -0,0 +1,28 @@
+#ifndef __CONFIG_QI_LB60_H
+#define __CONFIG_QI_LB60_H
+
+#include <configs/nanonote.h>
+
+#define CONFIG_QI_LB60 1
+
+//#define DEBUG
+#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
+#define CONFIG_BOOTARGSFROMSD "mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait"
+#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
+#define CONFIG_BOOTCOMMANDFROMSD "mmc init; ext2load mmc 0 0x80600000 /boot/uImage; bootm"
+
+/* SDRAM paramters */
+#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
+#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
+#define SDRAM_ROW 13 /* Row address: 11 to 13 */
+#define SDRAM_COL 9 /* Column address: 8 to 12 */
+#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
+
+/* SDRAM Timings, unit: ns */
+#define SDRAM_TRAS 45 /* RAS# Active Time */
+#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
+#define SDRAM_TPC 20 /* RAS# Precharge Time */
+#define SDRAM_TRWL 7 /* Write Latency Time */
+#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
+
+#endif
--
1.7.0.4
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