[U-Boot] [PATCH 12/15] powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code

[Kumar Gala]

Remove duplicated code in P1_P2_RDB boards and utliize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
 board/freescale/p1_p2_rdb/law.c |    6 +---
 board/freescale/p1_p2_rdb/pci.c |   64 +++++---------------------------------
 2 files changed, 10 insertions(+), 60 deletions(-)

diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c
index 1320d5d..4c80fa6 100644
--- a/board/freescale/p1_p2_rdb/law.c
+++ b/board/freescale/p1_p2_rdb/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -26,10 +26,6 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
index 2034459..ccfc996 100644
--- a/board/freescale/p1_p2_rdb/pci.c
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -32,65 +32,19 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
+static const char *slot_names[] = {
+	[PCIE1] = "Slot 2",
+	[PCIE2] = "Slot 1",
+};
 
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
+const char *board_serdes_name(enum srds_prtcl device)
+{
+	return slot_names[device];
+}
 
 void pci_init_board(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[2];
-	u32 devdisr, pordevsr;
-	int first_free_busno = 0;
-	int num = 0;
-
-	int pcie_ep, pcie_configured;
-
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-
-	puts("\n");
-#ifdef CONFIG_PCIE2
-	pcie_configured = is_serdes_configured(PCIE2);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-		printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-	} else {
-		printf("PCIE2: disabled\n");
-	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-		printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE1: disabled\n");
-	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
+	fsl_pcie_init_board(0);
 }
 
 void ft_pci_board_setup(void *blob)
-- 
1.6.0.6