[U-Boot] [RFC PATCH 3/8] OMAP3: and nand_spl support

[John Rigby]

Signed-off-by: John Rigby <john.rigby at linaro.org>
---
 arch/arm/cpu/armv7/omap3/board.c         |    4 ++++
 arch/arm/cpu/armv7/omap3/clock.c         |    3 +++
 arch/arm/cpu/armv7/omap3/gpio.c          |    5 +++++
 arch/arm/cpu/armv7/omap3/lowlevel_init.S |    2 +-
 arch/arm/cpu/armv7/omap3/mem.c           |    2 ++
 arch/arm/cpu/armv7/omap3/sys_info.c      |    6 ++++--
 6 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 6c2a132..e0ac010 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -166,6 +166,7 @@ void s_init(void)
 
 	try_unlock_memory();
 
+#ifndef CONFIG_NAND_SPL
 	/*
 	 * Right now flushing at low MPU speed.
 	 * Need to move after clock init
@@ -187,6 +188,7 @@ void s_init(void)
 	 */
 	if (get_device_type() == GP_DEVICE)
 		setup_auxcr();
+#endif /* !CONFIG_NAND_SPL */
 
 	set_muxconf_regs();
 	delay(100);
@@ -243,6 +245,7 @@ void abort(void)
 {
 }
 
+#ifndef CONFIG_NAND_SPL
 #ifdef CONFIG_NAND_OMAP_GPMC
 /******************************************************************************
  * OMAP3 specific command to switch between NAND HW and SW ecc
@@ -292,3 +295,4 @@ int checkboard (void)
 	return 0;
 }
 #endif	/* CONFIG_DISPLAY_BOARDINFO */
+#endif /* CONFIG_NAND_SPL */
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 2238c52..d44d327 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -34,6 +34,9 @@
 #include <environment.h>
 #include <command.h>
 
+#ifdef CONFIG_NAND_SPL
+#define is_running_in_flash() 0
+#endif
 /******************************************************************************
  * get_sys_clk_speed() - determine reference oscillator speed
  *                       based on known 32kHz clock and gptimer.
diff --git a/arch/arm/cpu/armv7/omap3/gpio.c b/arch/arm/cpu/armv7/omap3/gpio.c
index aeb6066..f276e89 100644
--- a/arch/arm/cpu/armv7/omap3/gpio.c
+++ b/arch/arm/cpu/armv7/omap3/gpio.c
@@ -40,6 +40,11 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 
+#ifdef CONFIG_NAND_SPL
+/* in the early stage of NAND flash booting, printf() is not available */
+#define printf(fmt, args...)
+#endif
+
 static struct gpio_bank gpio_bank_34xx[6] = {
 	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
 	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 109481e..b19e54a 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -35,7 +35,7 @@
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
 
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_NAND_U_BOOT)
 /**************************************************************************
  * cpy_clk_code: relocates clock code into SRAM where its safer to execute
  * R1 = SRAM destination address.
diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c
index bd914b0..71c138d 100644
--- a/arch/arm/cpu/armv7/omap3/mem.c
+++ b/arch/arm/cpu/armv7/omap3/mem.c
@@ -79,6 +79,7 @@ static const u32 gpmc_onenand[GPMC_MAX_REG] = {
 
 #endif
 
+#ifndef CONFIG_NAND_SPL
 /********************************************************
  *  mem_ok() - test used to see if timings are correct
  *             for a part. Helps in guessing which part
@@ -102,6 +103,7 @@ u32 mem_ok(u32 cs)
 	else
 		return 1;
 }
+#endif
 
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size)
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index 549ac19..2f06a7c 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -33,6 +33,7 @@
 
 extern omap3_sysinfo sysinfo;
 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+#ifndef CONFIG_NAND_SPL
 static char *rev_s[CPU_3XX_MAX_REV] = {
 				"1.0",
 				"2.0",
@@ -42,7 +43,6 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
 				"UNKNOWN",
 				"UNKNOWN",
 				"3.1.2"};
-
 /*****************************************************************
  * dieid_num_r(void) - read and set die ID
  *****************************************************************/
@@ -68,6 +68,7 @@ void dieid_num_r(void)
 
 	printf("Die ID #%s\n", uid_s);
 }
+#endif /* !CONFIG_NAND_SPL */
 
 /******************************************
  * get_cpu_type(void) - extract cpu info
@@ -214,7 +215,6 @@ u32 is_running_in_flash(void)
 {
 	if (get_base() < 4)
 		return 1;	/* in FLASH */
-
 	return 0;		/* running in SRAM or SDRAM */
 }
 
@@ -259,6 +259,7 @@ u32 get_device_type(void)
 	return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
 }
 
+#ifndef CONFIG_NAND_SPL
 #ifdef CONFIG_DISPLAY_CPUINFO
 /**
  * Print CPU information
@@ -351,3 +352,4 @@ int print_cpuinfo (void)
 	return 0;
 }
 #endif	/* CONFIG_DISPLAY_CPUINFO */
+#endif /* !CONFIG_NAND_SPL */
-- 
1.7.3.1.120.g38a18