[U-Boot] [PATCH] DaVinci DM6467: Fix Build Error

[s-paulraj at ti.com]

From: Sandeep Paulraj <s-paulraj at ti.com>

This commit fixes build errors on the DM6467 port.


Signed-off-by: Sandeep Paulraj <s-paulraj at ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/cpu.c |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
index fc3551c..340c5be 100644
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c
@@ -60,6 +60,12 @@
 #define DDR_PLLDIV	PLLC_PLLDIV1
 #endif
 
+#ifdef CONFIG_SOC_DM646X
+#define DSP_PLLDIV	PLLC_PLLDIV1
+#define ARM_PLLDIV	PLLC_PLLDIV2
+#define DDR_PLLDIV	PLLC_PLLDIV1
+#endif
+
 #ifdef CONFIG_SOC_DA8XX
 const dv_reg * const sysdiv[7] = {
 	&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
@@ -145,7 +151,11 @@ static inline unsigned pll_postdiv(volatile void *pllbase)
 static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
 {
 	volatile void	*pllbase = (volatile void *) pll_addr;
+#ifdef CONFIG_SOC_DM646X
+	unsigned	base = CFG_REFCLK_FREQ / 1000;
+#else
 	unsigned	base = CONFIG_SYS_HZ_CLOCK / 1000;
+#endif
 
 	/* the PLL might be bypassed */
 	if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
@@ -176,6 +186,12 @@ int print_cpuinfo(void)
 	return 0;
 }
 
+#ifdef DAVINCI_DM6467EVM
+unsigned int davinci_arm_clk_get()
+{
+	return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
+}
+#endif
 #endif
 
 /*
-- 
1.6.0.4