[U-Boot] TI Davinci and MUSB

[Wolfgang Denk]

Dear "Gupta, Ajay Kumar",

In message <19F8576C6E063C45BE387C64729E7394044A776008 at dbde02.ent.ti.com> you wrote:
>
> Opps, there are actually 32 intermediate register each of 32 bits.
> 
> So the correct one is as Neal suggested.
> 
> - u32 reserved[0x20];
> + u32 reserved[020/4];

0x20 / 4 = 8

020 / 4 = 4 

Best regards,

Wolfgang Denk

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