[U-Boot] [PATCH 1/3] add support for arm926ejs-based pollux CPU
Brian Cavagnolo
brian at cozybit.com
Tue Jun 1 20:42:28 CEST 2010
Signed-off-by: Brian Cavagnolo <brian at cozybit.com>
Signed-off-by: Andrey Yurovsky <yurovsky at gmail.com>
---
arch/arm/cpu/arm926ejs/pollux/Makefile | 51 ++++++++
arch/arm/cpu/arm926ejs/pollux/reset.S | 49 ++++++++
arch/arm/cpu/arm926ejs/pollux/timer.c | 190 +++++++++++++++++++++++++++++
arch/arm/include/asm/arch-pollux/clkpwr.h | 83 +++++++++++++
arch/arm/include/asm/arch-pollux/gpio.h | 143 ++++++++++++++++++++++
arch/arm/include/asm/arch-pollux/reg.h | 39 ++++++
arch/arm/include/asm/arch-pollux/timer.h | 59 +++++++++
arch/arm/include/asm/arch-pollux/uart.h | 105 ++++++++++++++++
8 files changed, 719 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/pollux/Makefile
create mode 100644 arch/arm/cpu/arm926ejs/pollux/reset.S
create mode 100644 arch/arm/cpu/arm926ejs/pollux/timer.c
create mode 100644 arch/arm/include/asm/arch-pollux/clkpwr.h
create mode 100644 arch/arm/include/asm/arch-pollux/gpio.h
create mode 100644 arch/arm/include/asm/arch-pollux/reg.h
create mode 100644 arch/arm/include/asm/arch-pollux/timer.h
create mode 100644 arch/arm/include/asm/arch-pollux/uart.h
diff --git a/arch/arm/cpu/arm926ejs/pollux/Makefile b/arch/arm/cpu/arm926ejs/pollux/Makefile
new file mode 100644
index 0000000..32803ff
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pollux/Makefile
@@ -0,0 +1,51 @@
+# (C) Copyright 2010 cozybit, Inc
+# Brian Cavagnolo <brian at cozybit.com>
+#
+# Derived from versatile cpu support:
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS = timer.o
+SOBJS = reset.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/pollux/reset.S b/arch/arm/cpu/arm926ejs/pollux/reset.S
new file mode 100644
index 0000000..a66a89f
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pollux/reset.S
@@ -0,0 +1,49 @@
+/* (C) Copyright 2010 cozybit, Inc
+ * Brian Cavagnolo <brian at cozybit.com>
+ *
+ * Derived from versatile cpu support:
+ *
+ * armboot - Startup Code for ARM926EJS CPU-core
+ *
+ * Copyright (c) 2003 Texas Instruments
+ *
+ * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ * Copyright (c) 2001 Marius Gröger <mag at sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu at sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <garyj at denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2 at ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij at ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ .align 5
+.globl reset_cpu
+reset_cpu:
+ ldr r1, rstctl1 /* get clkm1 reset ctl */
+ mov r3, #0x0
+ strh r3, [r1] /* clear it */
+ mov r3, #0x8
+ strh r3, [r1] /* force dsp+arm reset */
+_loop_forever:
+ b _loop_forever
+
+rstctl1:
+ .word 0xfffece10
diff --git a/arch/arm/cpu/arm926ejs/pollux/timer.c b/arch/arm/cpu/arm926ejs/pollux/timer.c
new file mode 100644
index 0000000..fc6c699
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pollux/timer.c
@@ -0,0 +1,190 @@
+/* (C) Copyright 2010 cozybit, Inc
+ * Brian Cavagnolo <brian at cozybit.com>
+ *
+ * (C) Copyright 2007 Leapfrog, Inc
+ *
+ * Derived from versatile cpu support:
+ *
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger at sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu at sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj at denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin at arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/reg.h>
+#include <asm/arch/timer.h>
+
+#ifndef CONFIG_SYS_TIMERBASE
+#error "Please define CONFIG_SYS_TIMERBASE to a suitable TIMERx_BASE"
+#endif
+#define TIMERBASE CONFIG_SYS_TIMERBASE
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+static ulong inline read_timer(void)
+{
+ REG32(TIMERBASE + TMRCONTROL) |= (1<<LDCNT);
+ return REG32(TIMERBASE + TMRMATCH);
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init (void)
+{
+ REG32(TIMERBASE + TMRCLKENB) = (1<<TCLKMODE)|(1<<TCLKGENENB);
+ REG32(TIMERBASE + TMRCOUNT) = 0;
+ REG32(TIMERBASE + TMRMATCH) = TIMER_LOAD_VAL;
+ REG32(TIMERBASE + TMRCONTROL) |= (1<<RUN);
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void __udelay (unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
+ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo /= 1000; /* finish normalize. */
+ }else{ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CONFIG_SYS_HZ;
+ tmo /= (1000*1000);
+ }
+
+ tmp = get_timer (0); /* get current timestamp */
+ if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */
+ reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */
+ else
+ tmo += tmp; /* else, set advancing stamp wake up time */
+
+ while (get_timer_masked () < tmo)/* loop till event */
+ /*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+ /* reset time */
+ lastdec = read_timer(); /* capure current decrementer value time */
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked (void)
+{
+ ulong now = read_timer(); /* current tick value */
+
+ if (lastdec >= now) { /* normal mode (non roll) */
+ /* normal mode */
+ timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
+ } else { /* we have overflow of the count down timer */
+ /* nts = ts + ld + (TLV - now)
+ * ts=old stamp, ld=time that passed before passing through -1
+ * (TLV-now) amount of time after passing though -1
+ * nts = new "advancing time stamp"...it could also roll and cause problems.
+ */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+ ulong tmo;
+ ulong endtime;
+ signed long diff;
+
+ if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
+ tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
+ tmo /= 1000; /* finish normalize. */
+ } else { /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CONFIG_SYS_HZ;
+ tmo /= (1000*1000);
+ }
+
+ endtime = get_timer_masked () + tmo;
+
+ do {
+ ulong now = get_timer_masked ();
+ diff = endtime - now;
+ } while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+
+ tbclk = CONFIG_SYS_HZ;
+ return tbclk;
+}
diff --git a/arch/arm/include/asm/arch-pollux/clkpwr.h b/arch/arm/include/asm/arch-pollux/clkpwr.h
new file mode 100644
index 0000000..d6e97d2
--- /dev/null
+++ b/arch/arm/include/asm/arch-pollux/clkpwr.h
@@ -0,0 +1,83 @@
+/* (C) Copyright 2010 cozybit, Inc.
+ * Brian Cavagnolo <brian at cozybit.com>
+ *
+ * (C) Copyright 2007 Leapfrog, Inc.
+ * Andrey Yurovsky" <yurovsky at gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CLKPWR_H__
+#define __CLKPWR_H__
+
+/* Clock and Power Control Registers */
+#define CLKPWR_BASE 0xC000F000
+#define CLKMODEREG (CLKPWR_BASE + 0x000)
+#define PLLSETREG0 (CLKPWR_BASE + 0x004)
+#define PLLSETREG1 (CLKPWR_BASE + 0x008)
+#define GPIOWAKEUPENB (CLKPWR_BASE + 0x040)
+#define RTCWAKEUPENB (CLKPWR_BASE + 0x044)
+#define GPIOWAKEUPRISEENB (CLKPWR_BASE + 0x048)
+#define GPIOWAKEUPFALLENB (CLKPWR_BASE + 0x04C)
+#define GPIOPEND (CLKPWR_BASE + 0x050)
+#define INTPENDSPAD (CLKPWR_BASE + 0x058)
+#define PWRRSTSTATUS (CLKPWR_BASE + 0x05C)
+#define INTENB (CLKPWR_BASE + 0x060)
+#define PWRMODE (CLKPWR_BASE + 0x07C)
+#define PADSTRENGTHGPIOAL (CLKPWR_BASE + 0x100)
+#define PADSTRENGTHGPIOAH (CLKPWR_BASE + 0x104)
+#define PADSTRENGTHGPIOBL (CLKPWR_BASE + 0x108)
+#define PADSTRENGTHGPIOBH (CLKPWR_BASE + 0x10C)
+#define PADSTRENGTHGPIOCL (CLKPWR_BASE + 0x110)
+#define PADSTRENGTHGPIOCH (CLKPWR_BASE + 0x114)
+#define PADSTRENGTHBUS (CLKPWR_BASE + 0x118)
+
+/* Clock Mode Register (CLKMODEREG) */
+#define PLLPWDN1 30
+#define CLKSELBCLK 24
+#define CLKDIV1BCLK 20
+#define CLKDIV2CPU0 6
+#define CLKSELCPU0 4
+#define CLKDIVCPU0 0
+
+/* PLL0/PLL1 Setting Register (PLLSETREG0/PLLSETREG1) */
+#define PDIV 18
+#define MDIV 8
+#define SDIV 0
+
+/* convenience macro for setting PLL */
+#define PLL_REG(m, p, s) \
+ (((unsigned int)(m) << MDIV) | \
+ ((unsigned int)(p) << PDIV) | \
+ ((unsigned int)(s) << SDIV))
+
+/* Power Mode Control Register (PWRMODE) */
+#define CHGPLL 15
+#define GPIOSWRSTENB 13
+#define SWRST 12
+#define LASTPWRMODE 4
+#define CURPWRMODE 0
+
+/* Interrupt Pending & Scratch Pad Register (INTPENDSPAD) */
+#define BATFW 14
+#define GPIORESETW 13
+#define WATCHDOGRSTW 12
+#define POWERONRSTW 11
+
+#endif /* __CLKPWR_H__ */
diff --git a/arch/arm/include/asm/arch-pollux/gpio.h b/arch/arm/include/asm/arch-pollux/gpio.h
new file mode 100644
index 0000000..f6ddd1b
--- /dev/null
+++ b/arch/arm/include/asm/arch-pollux/gpio.h
@@ -0,0 +1,143 @@
+/* (C) Copyright 2010 cozybit, Inc.
+ * Brian Cavagnolo <brian at cozybit.com>
+ *
+ * (C) Copyright 2007 Leapfrog, Inc.
+ * Andrey Yurovsky" <yurovsky at gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+/* GPIO registers */
+#define GPIO_BASE 0xC000A000
+
+#define GPIOAOUT (GPIO_BASE + 0x00)
+#define GPIOAOUTENB (GPIO_BASE + 0x04)
+#define GPIOADETMODE0 (GPIO_BASE + 0x08)
+#define GPIOADETMODE1 (GPIO_BASE + 0x0C)
+#define GPIOAINTENB (GPIO_BASE + 0x10)
+#define GPIOADET (GPIO_BASE + 0x14)
+#define GPIOAPAD (GPIO_BASE + 0x18)
+#define GPIOAPUENB (GPIO_BASE + 0x1C)
+#define GPIOAALTFN0 (GPIO_BASE + 0x20)
+#define GPIOAALTFN1 (GPIO_BASE + 0x24)
+
+#define GPIOBOUT (GPIO_BASE + 0x40)
+#define GPIOBOUTENB (GPIO_BASE + 0x44)
+#define GPIOBDETMODE0 (GPIO_BASE + 0x48)
+#define GPIOBDETMODE1 (GPIO_BASE + 0x4C)
+#define GPIOBINTENB (GPIO_BASE + 0x50)
+#define GPIOBDET (GPIO_BASE + 0x54)
+#define GPIOBPAD (GPIO_BASE + 0x58)
+#define GPIOBPUENB (GPIO_BASE + 0x5C)
+#define GPIOBALTFN0 (GPIO_BASE + 0x60)
+#define GPIOBALTFN1 (GPIO_BASE + 0x64)
+
+#define GPIOCOUT (GPIO_BASE + 0x80)
+#define GPIOCOUTENB (GPIO_BASE + 0x84)
+#define GPIOCDETMODE0 (GPIO_BASE + 0x88)
+#define GPIOCDETMODE1 (GPIO_BASE + 0x8C)
+#define GPIOCINTENB (GPIO_BASE + 0x90)
+#define GPIOCDET (GPIO_BASE + 0x94)
+#define GPIOCPAD (GPIO_BASE + 0x98)
+#define GPIOCPUENB (GPIO_BASE + 0x9C)
+#define GPIOCALTFN0 (GPIO_BASE + 0xA0)
+#define GPIOCALTFN1 (GPIO_BASE + 0xA4)
+
+/* GPIO Alive Registers */
+#define GPIO_ALIVE_BASE 0xC0019000
+#define ALIVEPWRGATEREG (GPIO_ALIVE_BASE + 0x00)
+#define ALIVEGPIORSTREG (GPIO_ALIVE_BASE + 0x04)
+#define ALIVEGPIOSETREG (GPIO_ALIVE_BASE + 0x08)
+#define ALIVEGPIOREADREG (GPIO_ALIVE_BASE + 0x0C)
+#define ALIVESCRATCHRSTREG (GPIO_ALIVE_BASE + 0x10)
+#define ALIVESCRATCHSETREG (GPIO_ALIVE_BASE + 0x14)
+#define ALIVESCRATCHREADREG (GPIO_ALIVE_BASE + 0x18)
+
+/* Alive GPIO Gate Register (ALIVEGPIOGATEREG) */
+#define NPOWERGATING 0
+
+/* Alive GPIO Register bit names
+ * same for ALIVEGPIORSTREG, ALIVEGPIOSETREG and ALIVEGPIOREADREG
+ */
+#define VDDPWRONSET 7
+
+/* Alive GPIO Read Register (ALIVEGPIOREADREG) */
+#define VDDPWRTOGGLE 8
+
+/* Current settings */
+#define GPIO_CURRENT_BASE 0xC000F100
+#define GPIOAPADSTRENGTH_L (GPIO_CURRENT_BASE + 0x00)
+#define GPIOAPADSTRENGTH_H (GPIO_CURRENT_BASE + 0x04)
+#define GPIOAPBDSTRENGTH_L (GPIO_CURRENT_BASE + 0x08)
+#define GPIOAPBDSTRENGTH_H (GPIO_CURRENT_BASE + 0x0C)
+#define GPIOAPCDSTRENGTH_L (GPIO_CURRENT_BASE + 0x10)
+#define GPIOAPCDSTRENGTH_H (GPIO_CURRENT_BASE + 0x14)
+
+/* Convenience macros for generating pin configurations for ALTFNn registers */
+#define ALTFN0_PIN_CFG(pin, cfg) ((cfg)<<((pin)*2))
+#define ALTFN0_PIN_MASK(pin) ALTFN0_PIN_CFG(pin, 0x3)
+#define ALTFN1_PIN_CFG(pin, cfg) ((cfg)<<((pin)*2-32))
+#define ALTFN1_PIN_MASK(pin) ALTFN1_PIN_CFG(pin, 0x3)
+
+
+enum gpio_port {
+ GPIO_PORT_A = 0,
+ GPIO_PORT_B,
+ GPIO_PORT_C,
+ GPIO_PORT_ALV,
+};
+
+/* Each pin can take one of three different functions */
+enum gpio_function {
+ GPIO_GPIOFN = 0,
+ GPIO_ALT1,
+ GPIO_ALT2,
+ GPIO_RESERVED,
+};
+
+/* Each port has 32 pins */
+enum gpio_pin {
+ GPIO_PIN0 = 0, GPIO_PIN1, GPIO_PIN2, GPIO_PIN3, GPIO_PIN4, GPIO_PIN5,
+ GPIO_PIN6, GPIO_PIN7, GPIO_PIN8, GPIO_PIN9, GPIO_PIN10, GPIO_PIN11,
+ GPIO_PIN12, GPIO_PIN13, GPIO_PIN14, GPIO_PIN15, GPIO_PIN16, GPIO_PIN17,
+ GPIO_PIN18, GPIO_PIN19, GPIO_PIN20, GPIO_PIN21, GPIO_PIN22, GPIO_PIN23,
+ GPIO_PIN24, GPIO_PIN25, GPIO_PIN26, GPIO_PIN27, GPIO_PIN28, GPIO_PIN29,
+ GPIO_PIN30, GPIO_PIN31,
+};
+
+/* Each pin can interrupt on one of four different events */
+enum gpio_interrupt_mode {
+ GPIO_IMODE_LOW_LEVEL = 0,
+ GPIO_IMODE_HIGH_LEVEL = 1,
+ GPIO_IMODE_FALLING_EDGE = 2,
+ GPIO_IMODE_RISING_EDGE = 3,
+};
+
+/* Each pin can drive with configurable current */
+enum gpio_current {
+ GPIO_CURRENT_2MA = 0,
+ GPIO_CURRENT_4MA = 1,
+ GPIO_CURRENT_6MA = 2,
+ GPIO_CURRENT_8MA = 3,
+};
+
+#endif /* __GPIO_H__ */
diff --git a/arch/arm/include/asm/arch-pollux/reg.h b/arch/arm/include/asm/arch-pollux/reg.h
new file mode 100644
index 0000000..fba6216
--- /dev/null
+++ b/arch/arm/include/asm/arch-pollux/reg.h
@@ -0,0 +1,39 @@
+/* (C) Copyright 2010 cozybit, Inc.
+ * Brian Cavagnolo <brian at cozybit.com>
+ *
+ * (C) Copyright 2007 Leapfrog, Inc.
+ * Andrey Yurovsky" <yurovsky at gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __REG_H__
+#define __REG_H__
+
+/* register access and manipulation helper macros */
+#define REG8(addr) (*((volatile unsigned char *)(addr)))
+#define REG16(addr) (*((volatile unsigned short *)(addr)))
+#define REG32(addr) (*((volatile unsigned long *)(addr)))
+
+#define BIT_SET(v,b) ((v) |= (1<<(b)))
+#define BIT_CLR(v,b) ((v) &= ~(1<<(b)))
+#define IS_SET(v,b) ((v) & (1<<(b)))
+#define IS_CLR(v,b) !((v) & (1<<(b)))
+
+#endif /* __REG_H__ */
diff --git a/arch/arm/include/asm/arch-pollux/timer.h b/arch/arm/include/asm/arch-pollux/timer.h
new file mode 100644
index 0000000..35a3363
--- /dev/null
+++ b/arch/arm/include/asm/arch-pollux/timer.h
@@ -0,0 +1,59 @@
+/* (C) Copyright 2010 cozybit, Inc.
+ * Brian Cavagnolo <brian at cozybit.com>
+ *
+ * (C) Copyright 2007 Leapfrog, Inc.
+ * Andrey Yurovsky" <yurovsky at gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+/* Timer base addresses */
+#define TIMER0_BASE 0xC0001800
+#define TIMER1_BASE 0xC0001880
+#define TIMER2_BASE 0xC0001900
+#define TIMER3_BASE 0xC0001980
+#define TIMER4_BASE 0xC0001A00
+
+/* Timer register offsets */
+#define TMRCOUNT 0x00
+#define TMRMATCH 0x04
+#define TMRCONTROL 0x08
+#define TMRCLKENB 0x40
+#define TMRCLKGEN 0x44
+
+/* Timer Control Register n (TMRCONTROLn) */
+#define LDCNT 6
+#define INTPEND 5
+#define TINTENB 4
+#define RUN 3
+#define WDENB 2
+#define SETCLK 0
+
+/* Timer Clock Generation Enable Register n (TMRCLKENBn) */
+#define TCLKMODE 3
+#define TCLKGENENB 2
+
+/* Timer Clock Generation Control Register n (TMRCLKGENn) */
+#define TCLKDIV 4
+#define TCLKSRCSEL 1
+
+#endif /* __TIMER_H__ */
diff --git a/arch/arm/include/asm/arch-pollux/uart.h b/arch/arm/include/asm/arch-pollux/uart.h
new file mode 100644
index 0000000..2b69a01
--- /dev/null
+++ b/arch/arm/include/asm/arch-pollux/uart.h
@@ -0,0 +1,105 @@
+/* (C) Copyright 2010 cozybit, Inc.
+ * Brian Cavagnolo <brian at cozybit.com>
+ *
+ * (C) Copyright 2007 Leapfrog, Inc.
+ * Andrey Yurovsky" <yurovsky at gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+/* UART base addresses */
+#define UART0_BASE 0xC0016000
+#define UART1_BASE 0xC0016080
+#define UART2_BASE 0xC0016800
+#define UART3_BASE 0xC0016880
+
+/* UART register offsets */
+#define LCON 0x00
+#define UCON 0x02
+#define FCON 0x04
+#define MCON 0x06
+#define TRSTATUS 0x08
+#define ESTATUS 0x0A
+#define FSTATUS 0x0C
+#define MSTATUS 0x0E
+#define THB 0x10
+#define RHB 0x12
+#define BRD 0x14
+#define TIMEOUTREG 0x16
+#define INTSTATUSREG 0x18
+#define UARTCLKENB 0x40
+#define UARTCLKGEN 0x44
+
+/* UART register bit definitions */
+
+/* LCON Register */
+#define SYNC_PENDCLR 7
+#define SIR_MODE 6
+#define PARITY_MODE 3
+#define STOPBIT 2
+#define WORD_LEN 0
+
+/* UCON Register */
+#define TX_INT 9
+#define RX_INT 8
+#define RX_TIMEOUT 7
+#define RX_ERRSTATUS 6
+#define LOOPBACK_MODE 5
+#define SEND_BREAK 4
+#define TRANS_MODE 2
+#define RECEIVE_MODE 0
+
+/* FCON Register */
+#define TX_FIFO_TRIGGER 6
+#define RX_FIFO_TRIGGER 4
+#define TX_FIFO_RESET 2
+#define RX_FIFO_RESET 1
+#define FIFO_EN 0
+
+/* MCON Register */
+#define HALF_CH_ENB 7
+#define SCRXENB 6
+#define SCTXENB 5
+#define AFC 4
+#define DTR_ACTIVE 1
+#define RTS_ACTIVE 0
+
+/* FSTATUS Register */
+#define RX_FIFO_ERROR 10
+#define TX_FIFO_FULL 9
+#define RX_FIFO_FULL 8
+#define TX_FIFO_COUNT 4
+#define RX_FIFO_COUNT 0
+
+/* TRSTATUS */
+#define TRANSMITTER_EMPTY 2
+#define TRANSMIT_BUFFER_EMPTY 1
+#define RECEIVE_BUFFER_DATA_READY 0
+
+/* UARTCLKENB */
+#define UARTCLKGENENB 2
+
+/* UARTCLKGEN */
+#define UARTCLKDIV 4
+#define UARTCLKSRCSEL 1
+
+#endif /* __UART_H__ */
--
1.6.0.4
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