[U-Boot] [PATCH 06/10] nds32: add nds32 board with include support
Macpaul Lin
macpaul at andestech.com
Fri Jun 11 11:34:40 CEST 2010
Add nds32 based board with include header files support.
Signed-off-by: Macpaul Lin <macpaul at andestech.com>
---
board/AndesTech/include/andes.h | 51 ++
board/AndesTech/include/chipset.h | 852 ++++++++++++++++++++++++++++++++++
board/AndesTech/include/flib_flash.h | 87 ++++
board/AndesTech/include/ftmac100.h | 257 ++++++++++
board/AndesTech/include/ftpci100.h | 238 ++++++++++
board/AndesTech/include/porting.h | 60 +++
board/AndesTech/include/serial.h | 175 +++++++
board/AndesTech/include/symbol.h | 107 +++++
8 files changed, 1827 insertions(+), 0 deletions(-)
create mode 100644 board/AndesTech/include/andes.h
create mode 100644 board/AndesTech/include/chipset.h
create mode 100644 board/AndesTech/include/flib_flash.h
create mode 100644 board/AndesTech/include/ftmac100.h
create mode 100644 board/AndesTech/include/ftpci100.h
create mode 100644 board/AndesTech/include/porting.h
create mode 100644 board/AndesTech/include/serial.h
create mode 100644 board/AndesTech/include/symbol.h
diff --git a/board/AndesTech/include/andes.h b/board/AndesTech/include/andes.h
new file mode 100644
index 0000000..1ab103b
--- /dev/null
+++ b/board/AndesTech/include/andes.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2006 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * define version number
+ */
+#define VERSION_MAJOR_NUM 0
+#define VERSION_MINOR_NUM 16
+#define VERSION_CLOCK SYSTEM_CLOCK
+
+/*
+ * define platform
+ */
+#define CONFIG_ADP_AG101_120_PLATFORM
+//#define CONFIG_ADP_AG101_110_PLATFORM
+
+/*
+ * define system clock
+ */
+//#define SYSTEM_CLOCK 16000000 //16.000000 MHz
+//#define SYSTEM_CLOCK 18432000 //18.432000 MHz
+//#define SYSTEM_CLOCK 22118400 //22.118400 MHz
+#define SYSTEM_CLOCK 83000000 //83.000000 MHz
+//#define SYSTEM_CLOCK 33000000 //83.000000 MHz
+//#define SYSTEM_CLOCK 36864000 //36.864000 MHz
+
+/*
+ * define flash bank
+ */
+#define CONFIG_FLASH_BANK 1 //bank 0,1,2,3,4,5,6,7
diff --git a/board/AndesTech/include/chipset.h b/board/AndesTech/include/chipset.h
new file mode 100644
index 0000000..c5cbf04
--- /dev/null
+++ b/board/AndesTech/include/chipset.h
@@ -0,0 +1,852 @@
+/*
+ * Copyright (C) 2006 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef CHIPSET_H
+#define CHIPSET_H
+
+/* DO NOT EDIT!! - this file automatically generated
+ * from .s file by awk -f s2h.awk
+ */
+/***********************************************************************
+ * Copyright Faraday Technology Corp 2002-2003. All rights reserved. *
+ *---------------------------------------------------------------------*
+ * Name:cpe.s *
+ * Description: ADP_AG101 board specfic define *
+ * Author: Fred Chien *
+ ***********************************************************************
+ */
+
+/*
+ * ADP_AG101 address map;
+ *
+ * +==========================================
+ * 0x00000000 | ROM
+ * |
+ * 0x00080000 |==========================================
+ * | SRAM
+ * |==========================================
+ * 0x10000000 | SDRAM
+ * 0x8FFFFFFF |
+ * |==========================================
+ * 0x90000000 |Controller's reg
+ * |
+ * |0x90100000 Arbiter/Decoder
+ * |0x90200000 SRAM controller reg
+ * |0x902ffffc Debug Numberic LED
+ * |0x90900000 SDRAM controller reg
+ * |0x90400000 DMA controller reg
+ * |0x90500000 AHB2APB bridge
+ * |0x90600000 Reserved
+ * |0x91000000-91F00000 DMA0-DMA15 Device;
+ * |0x92400000 DSP
+ * |0x92500000 Reserved
+ * |0x96500000 LCD
+ * |0x96600000 Bluetooth
+ * |0x96700000 MAC
+ * |0x96800000 PCI
+ * |0x96900000 USB2.0 host
+ * |0x98000000-9AFFFFFF APB Device;
+ * |
+ * 0x98000000 |==========================================
+ * | APB Device's Reg
+ * |
+ * |0x98000000 Reserved
+ * |0x98100000 Power Managemnet
+ * |0x98200000 UART1
+ * |0x98300000 UART2/IrDA
+ * |0x98400000 Timer
+ * |0x98500000 Watchdog Timer
+ * |0x98600000 RTC
+ * |0x98700000 GPIO
+ * |0x98800000 INTC
+ * |0x98900000 UART3
+ * |0x98A00000 I2C
+ * |0x98B00000 SSP1
+ * |0x98C00000 USB Device
+ * |0x98D00000 Compact Flash
+ * |0x98E00000 Secure Digital
+ * |0x98F00000 SMC
+ * |0x99000000 MS
+ * |0x99100000 SCI
+ * |0x99200000 ECP/EPP
+ * |0x99300000 KBC
+ * |0x99400000 I2S
+ * |0x99500000 AC97
+ * |0x99600000 SSP2
+ * |0x99700000 Mouse
+ * |0x9AFFFFFF Reserved
+ * |
+ * +==========================================
+ */
+
+/* -------------------------------------------------------------------------------
+ * ADP_AG101 system registers
+ * -------------------------------------------------------------------------------
+ * -------------------------------------------------------------------------------
+ * Decoder definitions
+ * -------------------------------------------------------------------------------
+ */
+
+#define AHB_SLAVE0_REG 0x00
+#define AHB_SLAVE1_REG 0x04
+#define AHB_SLAVE2_REG 0x08
+#define AHB_SLAVE3_REG 0x0c
+#define AHB_SLAVE4_REG 0x10
+#define AHB_SLAVE5_REG 0x14
+#define AHB_SLAVE6_REG 0x18
+#define AHB_SLAVE7_REG 0x1c
+#define AHB_SLAVE8_REG 0x20
+#define AHB_SLAVE9_REG 0x24
+#define AHB_SLAVE10_REG 0x28
+
+#define ADP_AG101_PRIORITY_REG 0x80
+#define ADP_AG101_DEFAULT_MASTER_REG 0x84
+#define ADP_AG101_REMAP_REG 0x88
+
+/* -------------------------------------------------------------------------------
+ * SRAM definitions
+ * -------------------------------------------------------------------------------
+ */
+
+#define SRAM_CONFIG0 0x00
+#define SRAM_TIME0 0x04
+#define SRAM_CONFIG1 0x08
+#define SRAM_TIME1 0x0C
+#define SRAM_CONFIG2 0x10
+#define SRAM_TIME2 0x14
+#define SRAM_CONFIG3 0x18
+#define SRAM_TIME3 0x1C
+#define SRAM_CONFIG4 0x20
+#define SRAM_TIME4 0x24
+#define SRAM_CONFIG5 0x28
+#define SRAM_TIME5 0x2C
+#define SRAM_CONFIG6 0x30
+#define SRAM_TIME6 0x34
+#define SRAM_CONFIG7 0x38
+#define SRAM_TIME7 0x3C
+#define SRAM_SHADOW 0x40
+#define SRAM_PARITY 0x44
+
+/* SRAM bank config register */
+
+#define SRAMBANK_ENABLE (1<<28)
+
+
+#define SRAMBNK_WPROT 0x800 /* write protect */
+
+#define SRAMBNK_TYPE1 0x400 /* synchrous */
+#define SRAMBNK_TYPE2 0x200 /* burst rom or pipeline depend on type 1 */
+#define SRAMBNK_TYPE3 0x100 /* write latency enable */
+
+/* bank size */
+#define SRAM_BNKSIZE_32K 0xb0
+#define SRAM_BNKSIZE_64K 0xc0
+#define SRAM_BNKSIZE_128K 0xd0
+#define SRAM_BNKSIZE_256K 0xe0
+#define SRAM_BNKSIZE_512K 0xf0
+#define SRAM_BNKSIZE_1M 0x00
+#define SRAM_BNKSIZE_2M 0x10
+#define SRAM_BNKSIZE_4M 0x20
+#define SRAM_BNKSIZE_8M 0x30
+#define SRAM_BNKSIZE_16M 0x40
+#define SRAM_BNKSIZE_32M 0x50
+
+
+/* bus width */
+#define SRAM_BNKMBW_8 0x0
+#define SRAM_BNKMBW_16 0x1
+#define SRAM_BNKMBW_32 0x2
+
+
+/* Timing parameter register */
+
+#define SRAM_RBE 0x100000 /* read byte enable */
+#define SRAM_AST1 0x40000 /* address setup time */
+#define SRAM_AST2 0x80000
+#define SRAM_AST3 0xc0000
+#define SRAM_CTW1 0x10000 /* chp select to write enable delay */
+#define SRAM_CTW2 0x20000 /* chp select to write enable delay */
+#define SRAM_CTW3 0x30000 /* chp select to write enable delay */
+
+
+
+
+/* -------------------------------------------------------------------------------
+ * SDRAM definitions
+ * -------------------------------------------------------------------------------
+ */
+
+
+
+#define SDRAM_TIME0 0x00
+#define SDRAM_TIME1 0x04
+#define SDRAM_CONFIG 0x08
+
+#define SDRAM_EXTBANK0 0x0C
+#define SDRAM_EXTBANK1 0x10
+#define SDRAM_EXTBANK2 0x14
+#define SDRAM_EXTBANK3 0x18
+#define SDRAM_EXTBANK4 0x1C
+#define SDRAM_EXTBANK5 0x20
+#define SDRAM_EXTBANK6 0x24
+#define SDRAM_EXTBANK7 0x28
+
+#define SDRAM_Arbiter 0x34
+
+/* Timing Parameter 0
+ * Active to precharge cycle
+ */
+#define SDRAM_TRAS_1 0x100000
+#define SDRAM_TRAS_2 0x200000
+#define SDRAM_TRAS_3 0x300000
+#define SDRAM_TRAS_4 0x400000
+#define SDRAM_TRAS_5 0x500000
+#define SDRAM_TRAS_6 0x600000
+#define SDRAM_TRAS_7 0x700000
+#define SDRAM_TRAS_8 0x800000
+
+/* Precharge cycle */
+#define SDRAM_TRP_1 0x010000
+#define SDRAM_TRP_2 0x020000
+#define SDRAM_TRP_3 0x030000
+#define SDRAM_TRP_4 0x040000
+#define SDRAM_TRP_5 0x050000
+#define SDRAM_TRP_6 0x060000
+#define SDRAM_TRP_7 0x070000
+#define SDRAM_TRP_8 0x080000
+
+/* RAS to CAS delay */
+#define SDRAM_TRCD_1 0x001000
+#define SDRAM_TRCD_2 0x002000
+#define SDRAM_TRCD_3 0x003000
+#define SDRAM_TRCD_4 0x004000
+#define SDRAM_TRCD_5 0x005000
+#define SDRAM_TRCD_6 0x006000
+#define SDRAM_TRCD_7 0x007000
+
+/* Auto refresh cycle */
+#define SDRAM_TRF_1 0x000100
+#define SDRAM_TRF_2 0x000200
+#define SDRAM_TRF_3 0x000300
+#define SDRAM_TRF_4 0x000400
+#define SDRAM_TRF_5 0x000500
+#define SDRAM_TRF_6 0x000600
+#define SDRAM_TRF_7 0x000700
+#define SDRAM_TRF_8 0x000800
+
+/* Write recovery time */
+#define SDRAM_TWR_1 0x000010
+#define SDRAM_TWR_2 0x000020
+#define SDRAM_TWR_3 0x000030
+
+/* CAS latency */
+#define SDRAM_TCL_1 0x1
+#define SDRAM_TCL_2 0x2
+#define SDRAM_TCL_3 0x3
+
+
+/* Timing Parameter 1 */
+
+/* Initial precharge times */
+#define SDRAM_INIPREC_1 0x100000
+#define SDRAM_INIPREC_2 0x200000
+#define SDRAM_INIPREC_3 0x300000
+#define SDRAM_INIPREC_4 0x400000
+#define SDRAM_INIPREC_5 0x500000
+#define SDRAM_INIPREC_6 0x600000
+#define SDRAM_INIPREC_7 0x700000
+#define SDRAM_INIPREC_8 0x800000
+
+
+/* Initial refresh times */
+#define SDRAM_INIREFT_1 0x10000
+#define SDRAM_INIREFT_2 0x20000
+#define SDRAM_INIREFT_3 0x30000
+#define SDRAM_INIREFT_4 0x40000
+#define SDRAM_INIREFT_5 0x50000
+#define SDRAM_INIREFT_6 0x60000
+#define SDRAM_INIREFT_7 0x70000
+#define SDRAM_INIREFT_8 0x80000
+
+/* Config reguister */
+#define ADP_AG101_REFRESH_TYPE 0x20 /* refresh type */
+#define ADP_AG101_IPREC 0x10 /* initial precharge flag */
+#define ADP_AG101_IREF 0x8 /* Initial refresh flag */
+#define ADP_AG101_ISMR 0x4 /* Start set mode register */
+#define ADP_AG101_PWDN 0x2 /* Power down mode */
+#define ADP_AG101_SREF 0x1 /* Self refresh mode when power down */
+
+/* External Bank Register define */
+
+/* data width */
+#define SDRAM_DDW4 (0x0 <<12)
+#define SDRAM_DDW8 (0x1 <<12)
+#define SDRAM_DDW16 (0x2 <<12)
+#define SDRAM_DDW32 (0x3 <<12)
+
+/* module size (bits) */
+#define SDRAM_DSZ_16M (0x00<<8)
+#define SDRAM_DSZ_64M (0x1<<8)
+#define SDRAM_DSZ_128M (0x2<<8)
+#define SDRAM_DSZ_256M (0x3<<8)
+
+/* Bus data width */
+#define SDRAM_BNK_WIDTH8 (0x0 <<4)
+#define SDRAM_BNK_WIDTH16 (0x1 <<4)
+#define SDRAM_BNK_WIDTH32 (0x2 <<4)
+
+/* Bank size */
+#define SDRAM_BNK_SIZE_1M 0x0
+#define SDRAM_BNK_SIZE_2M 0x1
+#define SDRAM_BNK_SIZE_4M 0x2
+#define SDRAM_BNK_SIZE_8M 0x3
+#define SDRAM_BNK_SIZE_16M 0x4
+#define SDRAM_BNK_SIZE_32M 0x5
+#define SDRAM_BNK_SIZE_64M 0x6
+#define SDRAM_BNK_SIZE_128M 0x7
+#define SDRAM_BNK_SIZE_256M 0x8
+
+/* -------------------------------------------------------------------------------
+ * AHB2APB Bridge definitions
+ * -------------------------------------------------------------------------------
+ */
+
+#define ADP_AG101_APB_BASE 0x90500000
+
+#define APB_SLAVE0_REG 0x0
+#define APB_SLAVE1_REG 0x4
+#define APB_SLAVE2_REG 0x8
+#define APB_SLAVE3_REG 0xc
+#define APB_SLAVE4_REG 0x10
+#define APB_SLAVE5_REG 0x14
+#define APB_SLAVE6_REG 0x18
+#define APB_SLAVE7_REG 0x1c
+#define APB_SLAVE8_REG 0x20
+#define APB_SLAVE9_REG 0x24
+#define APB_SLAVE10_REG 0x28
+#define APB_SLAVE11_REG 0x2c
+#define APB_SLAVE12_REG 0x30
+#define APB_SLAVE13_REG 0x34
+#define APB_SLAVE14_REG 0x38
+#define APB_SLAVE15_REG 0x3c
+#define APB_SLAVE16_REG 0x40
+#define APB_SLAVE17_REG 0x44
+#define APB_SLAVE18_REG 0x48
+#define APB_SLAVE19_REG 0x4c
+
+#define APB_DMA_SRC_A 0x80
+#define APB_DMA_DEST_A 0x84
+#define APB_DMA_CYCLE_A 0x88
+#define APB_DMA_CMD_A 0x8c
+#define APB_DMA_SRC_B 0x90
+#define APB_DMA_DEST_B 0x94
+#define APB_DMA_CYCLE_B 0x98
+#define APB_DMA_CMD_B 0x9c
+#define APB_DMA_SRC_C 0xa0
+#define APB_DMA_DEST_C 0xa4
+#define APB_DMA_CYCLE_C 0xa8
+#define APB_DMA_CMD_C 0xac
+#define APB_DMA_SRC_D 0xb0
+#define APB_DMA_DEST_D 0xb4
+#define APB_DMA_CYCLE_D 0xb8
+#define APB_DMA_CMD_D 0xbc
+
+
+/* -------------------------------------------------------------------------------
+ * APB Device definitions
+ * -------------------------------------------------------------------------------
+ */
+
+/* -------------------------------------------------------------------------------
+ * Timer definitions
+ * -------------------------------------------------------------------------------
+ */
+
+#define TIMER1_COUNT 0x0
+#define TIMER1_LOAD 0x4
+#define TIMER1_MATCH1 0x8
+#define TIMER1_MATCH2 0xC
+#define TIMER2_COUNT 0x10
+#define TIMER2_LOAD 0x14
+#define TIMER2_MATCH1 0x18
+#define TIMER2_MATCH2 0x1C
+#define TIMER3_COUNT 0x20
+#define TIMER3_LOAD 0x24
+#define TIMER3_MATCH1 0x28
+#define TIMER3_MATCH2 0x2C
+#define TIMER_CR 0x30
+
+#define PCLK 0
+#define EXTCLK 1
+
+/* -------------------------------------------------------------------------------
+ * GPIO definitions
+ * -------------------------------------------------------------------------------
+ */
+
+#define GPIO_DOUT_OFFSET 0x0
+#define GPIO_DIN_OFFSET 0X4
+#define GPIO_PINOUT_OFFSET 0x8
+#define GPIO_PIN_BYPASS 0XC
+#define GPIO_DATASET 0X10
+#define GPIO_DATACLR 0X14
+#define GPIO_INT_ENABLE 0X20
+#define GPIO_INT_SOURCE 0X24
+#define GPIO_INT_STATUS 0X28
+#define GPIO_INT_CLEAR 0X2C
+#define GPIO_INT_MODE 0X30
+#define GPIO_INT_BOUNCEENABLE 0X3C
+#define GPIO_INT_PRESCALE 0X40
+
+#define GPIO_NUM 32
+#define GPIO_EDGE 0
+#define GPIO_LEVEL 1
+#define SINGLE 0
+#define BOTH 1
+
+/* -------------------------------------------------------------------------------
+ * LED definitions
+ * -------------------------------------------------------------------------------
+ */
+
+#define LED_ON 0
+#define LED_OFF 1
+#define NUM_OF_LEDS 16
+#define DBG_LEDS (ADP_AG101_GPIO_BASE + GPIO_DOUT_OFFSET)
+#define LED_BASE DBG_LEDS
+
+
+/* -------------------------------------------------------------------------------
+ * Keyboard Mouse Interface (KMI) definitions
+ * -------------------------------------------------------------------------------
+ */
+
+#define MOUSE_ENABLE 0xF4
+
+#define KEYPAD_INT 0x04
+#define KEYBOARD_TXINT 0x02
+#define KEYBOARD_RXINT 0x01
+
+#define CLR_KEYPAD_INT 0x400
+#define CLR_KEYBOARD_TXINT 0x40
+#define CLR_KEYBOARD_RXINT 0x80
+
+
+/* -------------------------------------------------------------------------------
+ * Interrupt Controllers
+ * -------------------------------------------------------------------------------
+ */
+
+
+#define IRQ_SOURCE 0
+#define IRQ_MASK 0x04
+#define IRQ_CLEAR 0x08
+#define IRQ_MODE 0x0c
+#define IRQ_LEVEL 0x10
+#define IRQ_STATUS 0x14
+
+#define FIQ_SOURCE 0x20
+#define FIQ_MASK 0x24
+#define FIQ_CLEAR 0x28
+#define FIQ_MODE 0x2c
+#define FIQ_LEVEL 0x30
+#define FIQ_STATUS 0x34
+
+
+/* ADP_AG101 IRQ numbers definition */
+
+
+#define EXT_IRQ7 25
+#define EXT_IRQ6 24
+#define EXT_IRQ5 23
+#define EXT_IRQ4 22
+#define EXT_IRQ3 21
+#define EXT_IRQ2 20
+#define EXT_IRQ1 19
+//#define EXT_IRQ0 18
+#define IRQ_EXT 18 //old define
+
+#define IRQ_RTCALARM 17
+#define IRQ_WATCHDOG 16
+#define IRQ_TIMER3 15
+#define IRQ_TIMER2 14
+#define IRQ_GPIO 13
+#define IRQ_SMMC 12
+
+//#define IRQ_UART2 26 //new define
+#define IRQ_UART2 11 //old define
+//#define IRQ_RESERVE 11 //new define
+
+#define IRQ_UART1 10
+#define IRQ_MOUSE 9
+#define IRQ_SSP2 8
+#define IRQ_AC97 7
+#define IRQ_I2S 6
+#define IRQ_SDC 5
+#define IRQ_KBD 4
+#define IRQ_I2C 3
+#define IRQ_SSP1 2
+#define IRQ_CFC_DMA 1
+#define IRQ_CFC_CD 0
+
+
+/* ADP_AG101 FIQ number definition */
+
+#define FIQ_OFFSET 32
+
+#define EXT_FIQ8 (8+FIQ_OFFSET)
+#define EXT_FIQ7 (7+FIQ_OFFSET)
+#define EXT_FIQ6 (6+FIQ_OFFSET)
+#define EXT_FIQ5 (5+FIQ_OFFSET)
+
+//#define FIQ_IRDA2 (9+FIQ_OFFSET) //New define
+#define FIQ_IRDA2 (5+FIQ_OFFSET) //old define
+
+#define FIQ_IRDA1 (4+FIQ_OFFSET)
+#define FIQ_DMA (3+FIQ_OFFSET)
+#define FIQ_LCD (2+FIQ_OFFSET)
+#define FIQ_TIMER1 (1+FIQ_OFFSET)
+#define FIQ_RTCSEC (0+FIQ_OFFSET)
+
+
+/* Interrupt bit positions */
+
+#define MAXIRQNUM 31//18
+#define MAXFIQNUM 31//4
+#define NR_IRQS (MAXIRQNUM + 1)
+#define NR_FIQS (MAXFIQNUM + 1)
+
+#define LEVEL 0
+#define EDGE 1
+
+#define H_ACTIVE 0
+#define L_ACTIVE 1
+
+
+/* --------------------------------------------------------------------------
+ * SSP Controllers
+ * --------------------------------------------------------------------------
+ */
+
+
+#define I2S_RX_FIFO_OVER_RUN_INT (0x1)
+#define I2S_TX_FIFO_UNDER_RUN_INT (0x2)
+#define I2S_RX_FIFO_THRSD_INT (0x4)
+#define I2S_TX_FIFO_THRSD_INT (0x8)
+
+#define I2S_RX_DMA_ENABLE (0x10)
+#define I2S_TX_DMA_ENABLE (0x20)
+
+#define I2S_FSDIST_00 (0x0)
+#define I2S_FSDIST_01 (0x1 << 8)
+#define I2S_FSDIST_10 (0x2 << 8)
+#define I2S_FSDIST_11 (0x3 << 8)
+
+#define SSP_CONTROL0 0x0
+#define SSP_CONTROL1 0x4
+#define SSP_CONTROL2 0x8
+#define SSP_STATUS 0xC
+#define SSP_INT_CONTROL 0X10
+#define SSP_INT_STATUS 0x14
+#define SSP_DATA 0x18
+
+/* Control register 0 */
+
+#define SSP_FFMT_TI 0x0
+#define SSP_FFMT_MOTOR 0x1
+#define SSP_FFMT_NS 0x2
+#define SSP_FFMT_PHILP 0x3
+#define SSP_FFMT_INTEL 0x4
+
+#define SSP_FSDIST 0x1
+#define SSP_LBM 0x1 /* loopback mode */
+#define SSP_LSB 0x1 /* LSB first */
+#define SSP_FSPO_LOW 0x1 /* Frame sync atcive low */
+#define SSP_DATAPAD 0x1 /* data padding in front of serial data */
+
+#define SSP_OPM_MSST 0x3 /* Master stereo mode */
+#define SSP_OPM_MSMO 0x2 /* Master mono mode */
+#define SSP_OPM_SLST 0x1 /* Slave stereo mode */
+#define SSP_OPM_SLMO 0x0 /* Slave mono mode */
+
+#define SSP_SCLKPO_HIGH 0x1 /* SCLK Remain HIGH */
+#define SSP_SCLKPO_LOW 0x0 /* SCLK Remain LOW */
+#define SSP_SCLKPH_HALFCLK 0x1 /* Half CLK cycle */
+#define SSP_SCLKPH_ONECLK 0x0 /* One CLK cycle */
+
+
+/* Control Register 1 */
+
+#define SSP_PDL 0x00000000 /* paddinf data length */
+#define SSP_SDL 0x7 /* Serial data length(actual data length-1) */
+#define SSP_CLKDIV 0xf /* clk divider */
+
+/* Control Register 2 */
+
+#define SSP_ACCRST 0x1 /* AC-Link Cold Reset Enable */
+#define SSP_ACWRST 0x1 /* AC-Link Warm Reset Enable */
+#define SSP_TXFCLR 0x1 /* TX FIFO Clear */
+#define SSP_RXFCLR 0x1 /* RX FIFO Clear */
+#define SSP_TXDOE 0x1 /* TX Data Output Enable */
+#define SSP_SSPEN 0x1 /* SSP Enable */
+
+/* Status register
+ */
+#define SSP_TFVE 0x1f000 /* Tx FIFO Valid Entries */
+#define SSP_RFVE 0x1f0 /* Rx FIFO Valid Entries */
+
+#define SSP_BUSY 0x4 /* Busy for recv or tx */
+#define SSP_TFNF 0x2 /* TX FIFO Not Full */
+#define SSP_RFF 0x1 /* RX FIFO Full */
+
+
+/* Interrupr Control register */
+#define SSP_TXDMAEN 0x20 /* TX DMA Enable */
+#define SSP_RXDMAEN 0x10 /* RX DMA Enable */
+#define SSP_TFIEN 0x8 /* TX FIFO Int Enable */
+#define SSP_RFIEN 0x4 /* RX FIFO Int Enable */
+#define SSP_TFURIEN 0x2 /* TX FIFO Underrun int enable */
+#define SSP_RFURIEN 0x1 /* RX FIFO Underrun int enable */
+
+/* Interrupt Status register */
+#define SSP_TFTHI 0x8 /* TX FIFO Threshold Interrupt */
+#define SSP_RFTHI 0x4 /* RX FIFO Threshold Interrupt */
+#define TFURI 0x2 /* TX FIFO Underrun interrupt */
+#define RFURI 0x1 /* RX FIFO Underrun interrupt */
+
+#define MAX_SSP 0x4 /* ssp device number(include AC97 and I2S) */
+
+
+/* -------------------------------------------------------------------------------
+ * I2C Controllers
+ * -------------------------------------------------------------------------------
+ */
+
+
+/* I2C Control register */
+
+
+#define I2C_ALIEN 0x2000 /* Arbitration lose */
+#define I2C_SAMIEN 0x1000 /* slave address match */
+#define I2C_STOPIEN 0x800 /* stop condition */
+#define I2C_BERRIEN 0x400 /* non ACK response */
+#define I2C_DRIEN 0x200 /* data receive */
+#define I2C_DTIEN 0x100 /* data transmit */
+#define I2C_TBEN 0x80 /* transfer byte enable */
+#define I2C_ACKNAK 0x40 /* ack sent */
+#define I2C_STOP 0x20 /* stop */
+#define I2C_START 0x10 /* start */
+#define I2C_GCEN 0x8 /* general call */
+#define I2C_SCLEN 0x4 /* enable clock */
+#define I2C_I2CEN 0x2 /* enable I2C */
+#define I2C_I2CRST 0x1 /* reset I2C */
+#define I2C_ENABLE (I2C_ALIEN|I2C_SAMIEN|I2C_STOPIEN|I2C_BERRIEN|I2C_DRIEN|I2C_DTIEN|I2C_SCLEN|I2C_I2CEN)
+
+
+/* I2C Status Register */
+
+#define I2C_CLRAL 0x400
+#define I2C_CLRGC 0x200
+#define I2C_CLRSAM 0x100
+#define I2C_CLRSTOP 0x80
+#define I2C_CLRBERR 0x40
+#define I2C_DR 0x20
+#define I2C_DT 0x10
+#define I2C_BB 0x8
+#define I2C_BUSY 0x4
+#define I2C_ACK 0x2
+#define I2C_RW 0x1
+
+
+/* I2C clock divided register */
+
+#define I2C_CLKCOUNT 0x3ff
+
+
+/* I2C slave address register */
+
+#define I2C_EN10 0x80000000 /* 10-bit address slave mode */
+#define I2C_SARMSB 0x380 /* mask for SAR msb when EN10=1 */
+#define I2C_SARLSB 0x7f /* mask for SAR lsb */
+
+/* Bus Monitor Register */
+
+#define I2C_SCL 0x2
+#define I2C_SDA 0x1
+
+/* -------------------------------------------------------------------------------
+ * DMA Controllers
+ * -------------------------------------------------------------------------------
+ */
+
+#define ADP_AG101_DMA_BASE 0x90400000
+
+ /* registers */
+#define DMA_INT 0x0
+#define DMA_INT_TC 0x4
+#define DMA_INT_TC_CLR 0x8
+#define DMA_INT_ERR 0xC
+#define DMA_INT_ERR_CLR 0x10
+#define DMA_TC 0x14
+#define DMA_ERR 0x18
+#define DMA_CH_EN 0x1C
+#define DMA_CH_BUSY 0x20
+#define DMA_CSR 0x24
+#define DMA_SYNC 0x28
+
+#define DMA_C0_DevRegBase 0x40
+#define DMA_C0_DevDtBase 0x80
+
+#define DMA_CH_CFG_REG_OFFSET 0x20
+#define DMA_C0_CSR 0x100
+#define DMA_C0_CFG 0x104
+#define DMA_C0_SrcAddr 0x108
+#define DMA_C0_DstAddr 0x10C
+#define DMA_C0_LLP 0x110
+#define DMA_C0_SIZE 0x114
+
+/* bit mapping of main configuration status register(CSR) */
+#define DMA_CSR_M1ENDIAN 0x00000004
+#define DMA_CSR_M0ENDIAN 0x00000002
+#define DMA_CSR_DMACEN 0x00000001
+
+/* bit mapping of channel control register */
+#define DMA_CSR_TC_MSK 0x80000000
+#define DMA_CSR_CHPRJ_HIGHEST 0x00C00000
+#define DMA_CSR_CHPRJ_2ND 0x00800000
+#define DMA_CSR_CHPRJ_3RD 0x00400000
+#define DMA_CSR_PRTO3 0x00200000
+#define DMA_CSR_PRTO2 0x00100000
+#define DMA_CSR_PRTO1 0x00080000
+#define DMA_CSR_SRC_BURST_SIZE_1 0x00000000
+#define DMA_CSR_SRC_BURST_SIZE_4 0x00010000
+#define DMA_CSR_SRC_BURST_SIZE_8 0x00020000
+#define DMA_CSR_SRC_BURST_SIZE_16 0x00030000
+#define DMA_CSR_SRC_BURST_SIZE_32 0x00040000
+#define DMA_CSR_SRC_BURST_SIZE_64 0x00050000
+#define DMA_CSR_SRC_BURST_SIZE_128 0x00060000
+#define DMA_CSR_SRC_BURST_SIZE_256 0x00070000
+
+#define DMA_CSR_ABT 0x00008000
+#define DMA_CSR_SRC_WIDTH_8 0x00000000
+#define DMA_CSR_SRC_WIDTH_16 0x00000800
+#define DMA_CSR_SRC_WIDTH_32 0x00001000
+
+#define DMA_CSR_DST_WIDTH_8 0x00000000
+#define DMA_CSR_DST_WIDTH_16 0x00000100
+#define DMA_CSR_DST_WIDTH_32 0x00000200
+
+#define DMA_CSR_MODE_NORMAL 0x00000000
+#define DMA_CSR_MODE_HANDSHAKE 0x00000080
+
+#define DMA_CSR_SRC_INCREMENT 0x00000000
+#define DMA_CSR_SRC_DECREMENT 0x00000020
+#define DMA_CSR_SRC_FIX 0x00000040
+
+#define DMA_CSR_DST_INCREMENT 0x00000000
+#define DMA_CSR_DST_DECREMENT 0x00000008
+#define DMA_CSR_DST_FIX 0x00000010
+
+#define DMA_CSR_SRC_SEL 0x00000004
+#define DMA_CSR_DST_SEL 0x00000002
+#define DMA_CSR_CH_ENABLE 0x00000001
+
+
+#define DMA_MAX_SIZE 0x10000
+
+
+/* -----------------------------------------------------------------------
+ * STMC Controllers
+ * -----------------------------------------------------------------------
+ */
+
+#define STMC_BANK_WRITE_PROTECT (0x1 << 11) // bit 11
+
+#define STMC_BANK_TYPE1_ASYNC (0x0) // bit 10
+#define STMC_BANK_TYPE1_SYNC (0x1 << 10) // bit 10
+
+#define STMC_BANK_TYPE2_ASYNC (0x0) // bit 9
+#define STMC_BANK_TYPE2_BURST_ROM (0x1 << 9) // bit 9
+#define STMC_BANK_TYPE2_NON_PIPE (0x0) // bit 9
+#define STMC_BANK_TYPE2_PIPE (0x1 << 9) // bit 9
+
+#define STMC_BANK_TYPE3_LATE_WRITE_D (0x0) // bit 8
+#define STMC_BANK_TYPE3_LATE_WRITE_E (0x1 << 8) // bit 8
+
+#define STMC_BANK_TM_AST0 (0x0)
+#define STMC_BANK_TM_AST1 (0x01 << 18) // bit 18-19
+#define STMC_BANK_TM_AST2 (0x02 << 18) // bit 18-19
+#define STMC_BANK_TM_AST3 (0x03 << 18) // bit 18-19
+
+#define STMC_BANK_TM_CTW1 (0x01 << 16) // bit 16-17
+#define STMC_BANK_TM_CTW2 (0x02 << 16) // bit 16-17
+#define STMC_BANK_TM_CTW3 (0x03 << 16) // bit 16-17
+
+#define STMC_BANK_TM_AT1_1 (0x01 << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_2 (0x02 << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_3 (0x03 << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_4 (0x04 << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_5 (0x05 << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_6 (0x06 << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_7 (0x07 << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_8 (0x08 << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_9 (0x09 << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_A (0x0A << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_B (0x0B << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_C (0x0C << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_D (0x0D << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_E (0x0E << 12) // bit 12-15
+#define STMC_BANK_TM_AT1_F (0x0F << 12) // bit 12-15
+
+#define STMC_BANK_TM_AT2_1 (0x01 << 8) // bit 9-8
+#define STMC_BANK_TM_AT2_2 (0x02 << 8) // bit 9-8
+#define STMC_BANK_TM_AT2_3 (0x03 << 8) // bit 9-8
+
+#define STMC_BANK_TM_WTC1 (0x01 << 6) // bit 7-6
+#define STMC_BANK_TM_WTC2 (0x02 << 6) // bit 7-6
+#define STMC_BANK_TM_WTC3 (0x03 << 6) // bit 7-6
+
+#define STMC_BANK_TM_AHT1 (0x01 << 4) // bit 5-4
+#define STMC_BANK_TM_AHT2 (0x02 << 4) // bit 5-4
+#define STMC_BANK_TM_AHT3 (0x03 << 4) // bit 5-4
+
+#define STMC_BANK_TM_TRNA_1 (0x01) // bit 3-0
+#define STMC_BANK_TM_TRNA_2 (0x02) // bit 3-0
+#define STMC_BANK_TM_TRNA_3 (0x03) // bit 3-0
+#define STMC_BANK_TM_TRNA_4 (0x04) // bit 3-0
+#define STMC_BANK_TM_TRNA_5 (0x05) // bit 3-0
+#define STMC_BANK_TM_TRNA_6 (0x06) // bit 3-0
+#define STMC_BANK_TM_TRNA_7 (0x07) // bit 3-0
+#define STMC_BANK_TM_TRNA_8 (0x08) // bit 3-0
+#define STMC_BANK_TM_TRNA_9 (0x09) // bit 3-0
+#define STMC_BANK_TM_TRNA_A (0x0A) // bit 3-0
+#define STMC_BANK_TM_TRNA_B (0x0B) // bit 3-0
+#define STMC_BANK_TM_TRNA_C (0x0C) // bit 3-0
+#define STMC_BANK_TM_TRNA_D (0x0D) // bit 3-0
+#define STMC_BANK_TM_TRNA_E (0x0E) // bit 3-0
+#define STMC_BANK_TM_TRNA_F (0x0F) // bit 3-0
+
+/* END */
+
+#endif
diff --git a/board/AndesTech/include/flib_flash.h b/board/AndesTech/include/flib_flash.h
new file mode 100644
index 0000000..5a1b206
--- /dev/null
+++ b/board/AndesTech/include/flib_flash.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2006 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/***************************************************************************
+* Copyright Faraday Technology Corp 2002-2003. All rights reserved. *
+*--------------------------------------------------------------------------*
+* Name:symbol.h *
+* Description: Faraday code library define *
+* Author: Fred Chien *
+* Date: 2002/03/01 *
+* Version:1.0 *
+*--------------------------------------------------------------------------*
+***************************************************************************/
+
+#ifndef __ADP_AG101_FLASH_H
+#define __ADP_AG101_FLASH_H
+
+/*
+ * macronix flash
+ */
+#define MX_MANUFACT 0x00c20000 // macronix's manufacture id
+
+/*
+ * device id
+ */
+#define MX_ID_29LV008T 0x3e
+#define MX_ID_29LV008B 0x37
+#define MX_ID_26F128J3T 0x89
+
+/*
+ * SST flash
+ */
+#define SST_MANUFACT 0x00bf0000 // SST's manufacture id
+
+/*
+ * device id
+ */
+#define SST_ID_39VF080 0xd8
+#define SST_ID_39VF016 0xd9
+
+/*
+ * Intel flash
+ */
+#define INTEL_MANUFACT 0x00890000
+#define INTEL_ID_E28F128 0x18
+
+#define INTEL_E28F128_SIZE (0x1000000)
+#define INTEL_E28F128_SEC_SIZE (0x20000)
+
+#define FLASH_SINGLE (0x00)
+#define FLASH_DOUBLE (0x01)
+#define FLASH_FOUR (0x02)
+
+#define MX_Type (0x01)
+#define SST_Type (0x02)
+#define Intel_Type (0x03)
+
+#define PROGRAM_OK (1)
+#define PROGRAM_NOT_OK (-2)
+#define FLASH_PROGRAM_DELAY_CYCLE (50)
+#define FLASH_PROGRAM_LOOP_COUNTER (100)
+
+#endif
diff --git a/board/AndesTech/include/ftmac100.h b/board/AndesTech/include/ftmac100.h
new file mode 100644
index 0000000..9b6efc9
--- /dev/null
+++ b/board/AndesTech/include/ftmac100.h
@@ -0,0 +1,257 @@
+// --------------------------------------------------------------------
+// lmc83: modified from smc91111.h (2002-11-29)
+// --------------------------------------------------------------------
+
+#ifndef FTMAC100_H
+#define FTMAC100_H
+
+typedef unsigned char byte;
+typedef unsigned short word;
+typedef unsigned long int dword;
+
+// --------------------------------------------------------------------
+// structure for andesboot
+// --------------------------------------------------------------------
+
+#define ANDESBOOT
+#ifdef ANDESBOOT
+
+ #define MAX_ADDR_LEN 6
+ #define IFNAMSIZ 16
+ #define printk printf
+ #define mdelay udelay
+ #define spin_lock_irq
+ #define min(a, b) (((a) < (b)) ? (a) : (b))
+ #define kmalloc(a, b) malloc(a)
+ #define BUG() printf("faultal error\n"); for (;;)
+ #define virt_to_phys(a) (unsigned int)(a)
+
+ struct net_device
+ {
+ void *priv;
+ unsigned long base_addr;
+ int irq;
+ unsigned char dev_addr[MAX_ADDR_LEN]; /* hw address */
+ char name[IFNAMSIZ];
+
+ };
+
+ struct net_device_stats
+ {
+ unsigned long multicast;
+ };
+
+ typedef int spinlock_t;
+
+#endif
+
+// --------------------------------------------------------------------
+// FTMAC100 hardware related defenition
+// --------------------------------------------------------------------
+#ifdef CONFIG_ADP_AG101_110_PLATFORM
+#define NDS32_COMMON_FTMAC100_BASE 0x96700000
+#else
+#ifdef CONFIG_ADP_AG101_120_PLATFORM
+#define NDS32_COMMON_FTMAC100_BASE 0x90900000
+#endif
+#endif
+
+
+#define ISR_REG 0x00 // interrups status register
+#define IMR_REG 0x04 // interrupt maks register
+#define MAC_MADR_REG 0x08 // MAC address (Most significant)
+#define MAC_LADR_REG 0x0c // MAC address (Least significant)
+
+#define MAHT0_REG 0x10 // Multicast Address Hash Table 0 register
+#define MAHT1_REG 0x14 // Multicast Address Hash Table 1 register
+#define TXPD_REG 0x18 // Transmit Poll Demand register
+#define RXPD_REG 0x1c // Receive Poll Demand register
+#define TXR_BADR_REG 0x20 // Transmit Ring Base Address register
+#define RXR_BADR_REG 0x24 // Receive Ring Base Address register
+#define ITC_REG 0x28 // interrupt timer control register
+#define APTC_REG 0x2c // Automatic Polling Timer control register
+#define DBLAC_REG 0x30 // DMA Burst Length and Arbitration control register
+
+
+
+#define MACCR_REG 0x88 // MAC control register
+#define MACSR_REG 0x8c // MAC status register
+#define PHYCR_REG 0x90 // PHY control register
+#define PHYWDATA_REG 0x94 // PHY Write Data register
+#define FCR_REG 0x98 // Flow Control register
+#define BPR_REG 0x9c // back pressure register
+#define WOLCR_REG 0xa0 // Wake-On-Lan control register
+#define WOLSR_REG 0xa4 // Wake-On-Lan status register
+#define WFCRC_REG 0xa8 // Wake-up Frame CRC register
+#define WFBM1_REG 0xb0 // wake-up frame byte mask 1st double word register
+#define WFBM2_REG 0xb4 // wake-up frame byte mask 2nd double word register
+#define WFBM3_REG 0xb8 // wake-up frame byte mask 3rd double word register
+#define WFBM4_REG 0xbc // wake-up frame byte mask 4th double word register
+#define TM_REG 0xcc // test mode register
+
+
+
+// --------------------------------------------------------------------
+// ISR_REG and IMR_REG related
+// --------------------------------------------------------------------
+#define PHYSTS_CHG_bit (1UL<<9)
+#define AHB_ERR_bit (1UL<<8)
+#define RPKT_LOST_bit (1UL<<7)
+#define RPKT_SAV_bit (1UL<<6)
+#define XPKT_LOST_bit (1UL<<5)
+#define XPKT_OK_bit (1UL<<4)
+#define NOTXBUF_bit (1UL<<3)
+#define XPKT_FINISH_bit (1UL<<2)
+#define NORXBUF_bit (1UL<<1)
+#define RPKT_FINISH_bit (1UL<<0)
+
+
+// --------------------------------------------------------------------
+// APTC_REG related
+// --------------------------------------------------------------------
+typedef struct
+{
+ u32 RXPOLL_CNT:4;
+ u32 RXPOLL_TIME_SEL:1;
+ u32 Reserved1:3;
+ u32 TXPOLL_CNT:4;
+ u32 TXPOLL_TIME_SEL:1;
+ u32 Reserved2:19;
+}FTMAC100_APTCR_Status;
+
+
+// --------------------------------------------------------------------
+// MACCR_REG related
+// --------------------------------------------------------------------
+#define RX_BROADPKT_bit (1UL<<17) // Receiving broadcast packet
+#define RX_MULTIPKT_bit (1UL<<16) // receiving multicast packet
+#define FULLDUP_bit (1UL<<15) // full duplex
+#define CRC_APD_bit (1UL<<14) // append crc to transmit packet
+#define MDC_SEL_bit (1UL<<13) // set MDC as TX_CK/10
+#define RCV_ALL_bit (1UL<<12) // not check incoming packet's destination address
+#define RX_FTL_bit (1UL<<11) // Store incoming packet even its length is great than 1518 byte
+#define RX_RUNT_bit (1UL<<10) // Store incoming packet even its length is les than 64 byte
+#define HT_MULTI_EN_bit (1UL<<9)
+#define RCV_EN_bit (1UL<<8) // receiver enable
+#define XMT_EN_bit (1UL<<5) // transmitter enable
+#define CRC_DIS_bit (1UL<<4)
+#define LOOP_EN_bit (1UL<<3) // Internal loop-back
+#define SW_RST_bit (1UL<<2) // software reset/
+#define RDMA_EN_bit (1UL<<1) // enable DMA receiving channel
+#define XDMA_EN_bit (1UL<<0) // enable DMA transmitting channel
+
+
+// --------------------------------------------------------------------
+// Receive Ring descriptor structure
+// --------------------------------------------------------------------
+typedef struct
+{
+ // RXDES0
+ u32 ReceiveFrameLength:11; //0~10
+ u32 Reserved1:5; //11~15
+ u32 MULTICAST:1; //16
+ u32 BROARDCAST:1; //17
+ u32 RX_ERR:1; //18
+ u32 CRC_ERR:1; //19
+ u32 FTL:1;
+ u32 RUNT:1;
+ u32 RX_ODD_NB:1;
+ u32 Reserved2:5;
+ u32 LRS:1;
+ u32 FRS:1;
+ u32 Reserved3:1;
+ u32 RXDMA_OWN:1; // 1 ==> owned by FTMAC100, 0 ==> owned by software
+
+ // RXDES1
+ u32 RXBUF_Size:11;
+ u32 Reserved:20;
+ u32 EDOTR:1;
+
+ // RXDES2
+ u32 RXBUF_BADR;
+
+ u32 VIR_RXBUF_BADR; // not defined, we use it for maintaining the virtual address of receiving buffer
+
+} RX_DESC;
+
+
+typedef struct
+{
+ // TXDES0
+ u32 TXPKT_LATECOL:1;
+ u32 TXPKT_EXSCOL:1;
+ u32 Reserved1:29;
+ u32 TXDMA_OWN:1;
+
+ // TXDES1
+ u32 TXBUF_Size:11;
+ u32 Reserved2:16;
+ u32 LTS:1;
+ u32 FTS:1;
+ u32 TX2FIC:1;
+ u32 TXIC:1;
+ u32 EDOTR:1;
+
+ // RXDES2
+ u32 TXBUF_BADR;
+
+ u32 VIR_TXBUF_BADR; // Reserved, we use it for maintaining the virtual address of receiving buffer
+
+} TX_DESC;
+
+
+// waiting to do:
+#define TXPOLL_CNT 8
+#define RXPOLL_CNT 0
+
+#define OWNBY_SOFTWARE 0
+#define OWNBY_FTMAC100 1
+
+// --------------------------------------------------------------------
+// driver related definition
+// --------------------------------------------------------------------
+#define RXDES_NUM 64 // we defined 32 descriptors for receiving packets
+#define RX_BUF_SIZE 128 // each receiving buffer is 512 bytes
+#define TXDES_NUM 8
+#define TX_BUF_SIZE 2048
+
+
+/* store this information for the driver.. */
+struct ftmac100_local {
+
+ // these are things that the kernel wants me to keep, so users
+ // can find out semi-useless statistics of how well the card is
+ // performing
+ struct net_device_stats stats;
+
+ // Set to true during the auto-negotiation sequence
+ int autoneg_active;
+
+ // Address of our PHY port
+ u32 phyaddr;
+
+ // Type of PHY
+ u32 phytype;
+
+ // Last contents of PHY Register 18
+ u32 lastPhy18;
+
+ spinlock_t lock;
+ volatile RX_DESC *rx_descs; // receive ring base address
+ u32 rx_descs_dma; // receive ring physical base address
+ char *rx_buf; // receive buffer cpu address
+ int rx_buf_dma; // receive buffer physical address
+ int rx_idx; // current receive descriptor
+
+ volatile TX_DESC *tx_descs;
+ u32 tx_descs_dma;
+ char *tx_buf;
+ int tx_buf_dma;
+ int tx_idx;
+
+ int maccr_val;
+};
+
+#define FTMAC100_STROBE_TIME (20*HZ)
+
+#endif /* FTMAC100_H */
diff --git a/board/AndesTech/include/ftpci100.h b/board/AndesTech/include/ftpci100.h
new file mode 100644
index 0000000..ee98791
--- /dev/null
+++ b/board/AndesTech/include/ftpci100.h
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2006 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __PCI_H__
+#define __PCI_H__ 1
+
+#include <porting.h>
+#include <pci.h>
+
+/* Condition Definition */
+#define DEBUG_INFO_ENABLE 0x00
+//#define USE_IDSELECT_1234 0x00
+
+/* Slot Definition */
+#ifdef USE_IDSELECT_1234
+ #define SLOT_1 0x01
+ #define SLOT_2 0x02
+ #define SLOT_3 0x03
+ #define SLOT_4 0x04
+#else
+ #define SLOT_1 0x08
+ #define SLOT_2 0x09
+ #define SLOT_3 0x0A
+ #define SLOT_4 0x0B
+#endif
+
+
+#define PCI_BASE_CLASS_MASS_STORAGE 1
+#define PCI_BASE_CLASS_NETWORK 2
+#define PCI_BASE_CLASS_DISPLAY 3
+#define PCI_BASE_CLASS_MULTIMEDIA 4
+#define PCI_BASE_CLASS_MEMORY 5
+#define PCI_BASE_CLASS_BRIDGE 6
+#define PCI_BASE_CLASS_SIMPLE_COMMUNICATION 7
+#define PCI_BASE_CLASS_BASE_SYS_PERIPHERAL 8
+#define PCI_BASE_CLASS_INPUT 9
+#define PCI_BASE_CLASS_DOCK_STATION 10
+#define PCI_BASE_CLASS_PROCESSOR 11
+#define PCI_BASE_CLASS_SERIAL 12
+
+/* 7.Alignment Constants */
+#define PCI_MEM_SPACE_ALIGNMENT 0x10
+#define PCI_IO_SPACE_ALIGNMENT 0x4
+
+
+
+/*
+ * PCI Configuration Space Structures
+ */
+typedef struct
+{
+ /* offset 0x00 */
+ UINT32 VendorID:16;
+ UINT32 DeviceID:16;
+ /* offset 0x04 */
+ UINT32 Command:16;
+ UINT32 Status:16;
+ /* offset 0x08 */
+ UINT32 RevisionID:8;
+ UINT32 ClassCode:24;
+ /* offset 0x0c */
+ UINT32 CacheLineSize:8;
+ UINT32 LatencyTimer:8;
+ UINT32 HeaderType:8;
+ UINT32 BIST:8;
+ /* offset 0x10 - 0x24*/
+ UINT32 BaseAddrReg[6];
+ /* offset 0x28 */
+ UINT32 CardbusCISPointer;
+ /* offset 0x2c */
+ UINT32 SubsystemVendorID:16;
+ UINT32 SubsystemID:16;
+ /* offset 0x30 */
+ UINT32 ExpansionROMBaseAddr;
+ /* offset 0x34-0x38 */
+ UINT32 Reserved[2];
+ /* offset 0x3c */
+ UINT32 IntLine:8;
+ UINT32 IntPin:8;
+ UINT32 MinGnt:8;
+ UINT32 MaxLat:8;
+} PCIConfigSpaceStruct;
+
+
+
+/*
+ * u-boot header info for the Faraday FTPCI100 AHB-PCI Bridge.
+ *
+ * History:
+ * 2009.04.13 Init - Hill
+ */
+
+#define PCI_DEBUG_INFO 0
+
+#if PCI_DEBUG_INFO
+#define print_pci(format, arg...) printf("PCI DBG INFO: \r\n " format "\n", ## arg)
+#else
+#define print_pci(format, arg...) do {} while (0)
+#endif
+
+//ivan modified
+#define ADP_AG101_PCI_IO_BASE 0x90c00000 // ~1MB
+#define ADP_AG101_PCI_MEM_BASE 0xa0000000 // ~256MB
+
+#define PCI_CARD_IO_BASE (ADP_AG101_PCI_IO_BASE+0x1000)//0x90c00100
+#define PCI_CARD_MEM_BASE ADP_AG101_PCI_MEM_BASE// ADP_AG101_PCI_MEM_BASE
+#define PCI_CARD_MEM_TOTAL_SIZE 0x10000000
+
+#define PCI_BRIDGE_REGISTER_IO 0x00
+#define PCI_BRIDGE_REGISTER_AHB_PROTECTION 0x04
+#define PCI_BRIDGE_REGISTER_PCI_CONTROL_REGISTER 0x08
+#define PCI_BRIDGE_REGISTER_ERREN 0x0C
+#define PCI_BRIDGE_REGISTER_SOFT_RESET 0x10
+#define PCI_BRIDGE_REGISTER_ENABLE_64BIT 0x14
+#define PCI_BRIDGE_REGISTER_HIGHT_32BIT_ABR 0x18
+#define PCI_CONFIG_ADDR_REG 0x28
+#define PCI_CONFIG_DATA_REG 0x2C
+
+#define PCI_BRIDGE_CFG_SPACE_CONTROL 0x4C
+#define PCI_BRIDGE_CFG_INTABCD_STATUS 0x4F
+#define PCI_BRIDGE_CFG_INTMASK 0x4E
+#define PCI_BRIDGE_CFG_SPACE_MEM1_BA 0x80000050
+#define PCI_BRIDGE_CFG_SPACE_MEM2_BA 0x80000054
+#define PCI_BRIDGE_CFG_SPACE_MEM3_BA 0x80000058
+
+#define PCI_ENABLE_INTA_INTB_INTC_INTD 0x03C00000
+#define PCI_ALL_INTs_MASK 0x0FFF0000
+#define PCI_BRIDGE_MAX_INT_NUMBER 0x04
+#define PCI_DMA_MEM_REQUEST_FAIL 0xFFFFFFFF
+#define PCI_DMA_DEFAULT_SIZE 0x00
+
+/* disable INTs in u-boot */
+#define PCI_INT_USE_ACTIVE_H 0x01 //After 12/01/2002-->Use Active High
+
+#define PCI_BRIDGE_DMA_START_ADDRESS 0x02000000 //0x05000000
+#define PCI_BRIDGE_DMA_SIZE 0x10 //16M (SIZE)
+#define PCI_BRIDGE_DMA_START_SIZE_VALUE 0x02040000 //4=> 16M (SIZE)0x05040000
+#define PCI_BRIDGE_DMA_START_SIZE_256MB 0x02080000 //8=>256M (SIZE)0x05040000
+
+#define PCI_INBOUND_MEM_BASE 0 // DRAM Base Address
+#define PCI_INBOUND_MEM_1MB (0<<16)
+#define PCI_INBOUND_MEM_2MB (1<<16)
+#define PCI_INBOUND_MEM_4MB (2<<16)
+#define PCI_INBOUND_MEM_8MB (3<<16)
+#define PCI_INBOUND_MEM_16MB (4<<16)
+#define PCI_INBOUND_MEM_32MB (5<<16)
+#define PCI_INBOUND_MEM_64MB (6<<16)
+#define PCI_INBOUND_MEM_128MB (7<<16)
+#define PCI_INBOUND_MEM_256MB (8<<16)
+#define PCI_INBOUND_MEM_512MB (9<<16)
+#define PCI_INBOUND_MEM_1GB (0xA<<16)
+
+/* Configuration Space Header offset*/
+#define PCI_CSH_VENDOR_ID_REG 0x00
+#define PCI_CSH_DEVICE_ID_REG 0x02
+#define PCI_CSH_COMMAND_REG 0x04
+#define PCI_CSH_STATUS_REG 0x06
+#define PCI_CSH_REVISION_CLASS_REG 0x08
+#define PCI_CSH_CACHE_LINE_SIZE_REG 0x0C
+#define PCI_CSH_LATENCY_TIMER_REG 0x0D
+#define PCI_CSH_HEADER_TYPE_REG 0x0E
+#define PCI_CSH_BIST_REG 0x0F
+#define PCI_CSH_BASE_ADDR_REG 0x10
+
+#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
+
+/* PCI command status register bit mapping */
+#define PCI_CMD_IO_ENABLE 0x00000001
+#define PCI_CMD_MEM_ENABLE 0x00000002
+#define PCI_CMD_BUS_MASTER_ENABLE 0x00000004
+
+#define PCI_MAX_DEVICE_TYPE_NUM 0x13
+#define PCI_MAX_BAR_NUM 0x06
+#define PCI_MAX_BUS_NUM 0x03 // 256
+#define PCI_MAX_DEVICE_NUM 0x10 // 32
+#define PCI_MAX_FUNCTION_NUM 0x04 // 8
+#define PCI_MAX_REG_NUM 0x3c
+
+/*
+ * PCI Configuration Address Structures
+ */
+
+typedef struct {
+ UINT32 RegNum:8;
+ UINT32 FunNum:3;
+ UINT32 DevNum:5;
+ UINT32 BusNum:8;
+ UINT32 Always0:7;
+ UINT32 Enable:1;
+} PCIDeviceIDStruct;
+
+
+typedef struct {
+ UINT32 PciIOAddr;
+ UINT32 PciMem0Addr;
+ UINT32 PciMem1Addr;
+} PCIResourceMapStruct;
+
+typedef struct {
+ UINT8 *PCI_DMA_Start_Pointer;
+ UINT32 PCI_DMA_Size_Remain;
+ UINT32 PCI_DMA_Base_Address;
+} PCIBridgeDMAResourceMapStruct;
+
+/*
+ * exposed APIs
+ */
+void pci_init_board(void);
+
+int flib_read_byte(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, unsigned char *pu8Dat);
+int flib_read_word(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, unsigned short *pu16Dat);
+int flib_read_dword(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, unsigned long *pu32Dat);
+int flib_write_byte(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, unsigned char u8Dat);
+int flib_write_word(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, unsigned short u16Dat);
+int flib_write_dword(struct pci_controller *pPciHC, pci_dev_t PciDev, int where, unsigned long u32Dat);
+
+#endif
diff --git a/board/AndesTech/include/porting.h b/board/AndesTech/include/porting.h
new file mode 100644
index 0000000..c2bd151
--- /dev/null
+++ b/board/AndesTech/include/porting.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2006 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ADP_AG101_PORTING
+#define __ADP_AG101_PORTING
+
+#include <asm/types.h>
+//#include <adp-ag101.h>
+#include "chipset.h"
+#include "symbol.h"
+
+/*
+ * "1 word" in armboot ==> 2 bytes
+ * "1 word" in nds32 architecture ==> 4 bytes,
+ * When we should take care the follows when we port code to armboot
+ * inw" (nds32) should be replaced by "inl";
+ * "outw" (nds32) should be replaced by "outl"
+ */
+
+#ifndef u32
+ #define u32 unsigned long
+#endif
+
+#ifndef u16
+ #define u16 unsigned short
+#endif
+
+#ifndef u8
+ #define u8 unsigned char
+#endif
+
+#define cpe_inl(addr) (*((volatile u32 *)(addr)))
+#define cpe_inw(addr) (*((volatile u16 *)(addr)))
+#define cpe_inb(addr) (*((volatile u8 *)(addr)))
+#define cpe_outl(addr, value) (*((volatile u32 *)(addr)) = value)
+#define cpe_outw(addr, value) (*((volatile u16 *)(addr)) = value)
+#define cpe_outb(addr, value) (*((volatile u8 *)(addr)) = value)
+
+#endif
diff --git a/board/AndesTech/include/serial.h b/board/AndesTech/include/serial.h
new file mode 100644
index 0000000..5382c1b
--- /dev/null
+++ b/board/AndesTech/include/serial.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2006 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ADP_AG101_SERIAL_H
+#define __ADP_AG101_SERIAL_H
+
+/*
+ * define UART clock
+ */
+//#define UART_CLOCK 22118400 //22.118400 MHZ ASIC version
+//#define UART_CLOCK 18432000 //ASIC320, comes from faraday.h
+#define UART_CLOCK (18432000 * 20) / 25 // comes from andes.h (now merged into configs/ag101.h)
+//#define UART_CLOCK CONFIG_SYS_CLK_FREQ/2 // CONFIG_SYS_CLK_FREQ/2 FPGA version
+
+/*
+ * UART definitions
+ */
+#define SERIAL_THR 0x00 /* Transmitter Holding Register(Write).*/
+#define SERIAL_RBR 0x00 /* Receive Buffer register (Read).*/
+#define SERIAL_IER 0x04 /* Interrupt Enable register.*/
+#define SERIAL_IIR 0x08 /* Interrupt Identification register(Read).*/
+#define SERIAL_FCR 0x08 /* FIFO control register(Write).*/
+#define SERIAL_LCR 0x0C /* Line Control register.*/
+#define SERIAL_MCR 0x10 /* Modem Control Register.*/
+#define SERIAL_LSR 0x14 /* Line status register(Read) .*/
+#define SERIAL_MSR 0x18 /* Modem Status register (Read).*/
+#define SERIAL_SPR 0x1C /* Scratch pad register */
+#define SERIAL_DLL 0x0 /* Divisor Register LSB */
+#define SERIAL_DLM 0x4 /* Divisor Register MSB */
+#define SERIAL_PSR 0x8 /* Prescale Divison Factor */
+
+#define SERIAL_MDR 0x20
+#define SERIAL_ACR 0x24
+#define SERIAL_TXLENL 0x28
+#define SERIAL_TXLENH 0x2C
+#define SERIAL_MRXLENL 0x30
+#define SERIAL_MRXLENH 0x34
+#define SERIAL_PLR 0x38
+#define SERIAL_FMIIR_PIO 0x3C
+
+/* IER Register */
+#define SERIAL_IER_DR 0x1 /* Data ready Enable */
+#define SERIAL_IER_TE 0x2 /* THR Empty Enable */
+#define SERIAL_IER_RLS 0x4 /* Receive Line Status Enable */
+#define SERIAL_IER_MS 0x8 /* Modem Staus Enable */
+
+/* IIR Register */
+#define SERIAL_IIR_NONE 0x1 /* No interrupt pending */
+#define SERIAL_IIR_RLS 0x6 /* Receive Line Status */
+#define SERIAL_IIR_DR 0x4 /* Receive Data Ready */
+#define SERIAL_IIR_TIMEOUT 0xc /* Receive Time Out */
+#define SERIAL_IIR_TE 0x2 /* THR Empty */
+#define SERIAL_IIR_MODEM 0x0 /* Modem Status */
+
+/* FCR Register */
+#define SERIAL_FCR_FE 0x1 /* FIFO Enable */
+#define SERIAL_FCR_RXFR 0x2 /* Rx FIFO Reset */
+#define SERIAL_FCR_TXFR 0x4 /* Tx FIFO Reset */
+
+/* LCR Register */
+#define SERIAL_LCR_LEN5 0x0
+#define SERIAL_LCR_LEN6 0x1
+#define SERIAL_LCR_LEN7 0x2
+#define SERIAL_LCR_LEN8 0x3
+
+#define SERIAL_LCR_STOP 0x4
+#define SERIAL_LCR_EVEN 0x18 /* Even Parity */
+#define SERIAL_LCR_ODD 0x8 /* Odd Parity */
+#define SERIAL_LCR_PE 0x8 /* Parity Enable */
+#define SERIAL_LCR_SETBREAK 0x40 /* Set Break condition */
+#define SERIAL_LCR_STICKPARITY 0x20 /* Stick Parity Enable */
+#define SERIAL_LCR_DLAB 0x80 /* Divisor Latch Access Bit */
+
+/* LSR Register */
+#define SERIAL_LSR_DR 0x1 /* Data Ready */
+#define SERIAL_LSR_OE 0x2 /* Overrun Error */
+#define SERIAL_LSR_PE 0x4 /* Parity Error */
+#define SERIAL_LSR_FE 0x8 /* Framing Error */
+#define SERIAL_LSR_BI 0x10 /* Break Interrupt */
+#define SERIAL_LSR_THRE 0x20 /* THR Empty */
+#define SERIAL_LSR_TE 0x40 /* Transmitte Empty */
+#define SERIAL_LSR_DE 0x80 /* FIFO Data Error */
+
+/* MCR Register */
+#define SERIAL_MCR_DTR 0x1 /* Data Terminal Ready */
+#define SERIAL_MCR_RTS 0x2 /* Request to Send */
+#define SERIAL_MCR_OUT1 0x4 /* output 1 */
+#define SERIAL_MCR_OUT2 0x8 /* output2 or global interrupt enable */
+#define SERIAL_MCR_LPBK 0x10 /* loopback mode */
+
+/* MSR Register */
+#define SERIAL_MSR_DELTACTS 0x1 /* Delta CTS */
+#define SERIAL_MSR_DELTADSR 0x2 /* Delta DSR */
+#define SERIAL_MSR_TERI 0x4 /* Trailing Edge RI */
+#define SERIAL_MSR_DELTACD 0x8 /* Delta CD */
+#define SERIAL_MSR_CTS 0x10 /* Clear To Send */
+#define SERIAL_MSR_DSR 0x20 /* Data Set Ready */
+#define SERIAL_MSR_RI 0x40 /* Ring Indicator */
+#define SERIAL_MSR_DCD 0x80 /* Data Carrier Detect */
+
+/* MDR register */
+#define SERIAL_MDR_MODE_SEL 0x03
+#define SERIAL_MDR_UART 0x0
+#define SERIAL_MDR_SIR 0x1
+#define SERIAL_MDR_FIR 0x2
+
+/* ACR register */
+#define SERIAL_ACR_TXENABLE 0x1
+#define SERIAL_ACR_RXENABLE 0x2
+#define SERIAL_ACR_SET_EOT 0x4
+
+/*
+ * API
+ */
+#ifdef not_complete_yet
+extern UINT32 DebugSerialPort;
+extern UINT32 SystemSerialPort;
+#endif /* end_of_not */
+
+extern void fLib_SerialInit(UINT32 port, UINT32 baudrate, UINT32 parity,UINT32 num,UINT32 len);
+extern void fLib_SetSerialFifoCtrl(UINT32 port, UINT32 level, UINT32 resettx, UINT32 resetrx);
+extern void fLib_DisableSerialFifo(UINT32 port);
+extern void fLib_SetSerialInt(UINT32 port, UINT32 IntMask);
+
+extern char fLib_GetSerialChar(UINT32 port);
+extern void fLib_PutSerialChar(UINT32 port, char Ch);
+extern void fLib_PutSerialStr(UINT32 port, char *Str);
+
+extern void fLib_EnableSerialInt(UINT32 port, UINT32 mode);
+extern void fLib_DisableSerialInt(UINT32 port, UINT32 mode);
+
+extern void fLib_SerialRequestToSend(UINT32 port);
+extern void fLib_SerialStopToSend(UINT32 port);
+extern void fLib_SerialDataTerminalReady(UINT32 port);
+extern void fLib_SerialDataTerminalNotReady(UINT32 port);
+
+extern void fLib_SetSerialLineBreak(UINT32 port);
+extern void fLib_SetSerialLoopBack(UINT32 port,UINT32 onoff);
+extern UINT32 fLib_SerialIntIdentification(UINT32 port);
+
+extern UINT32 fLib_ReadSerialLineStatus(UINT32 port);
+extern UINT32 fLib_ReadSerialModemStatus(UINT32 port);
+
+extern void fLib_SetSerialMode(UINT32 port, UINT32 mode);
+extern void fLib_EnableIRMode(UINT32 port, UINT32 TxEnable, UINT32 RxEnable);
+
+extern void fLib_Modem_call(UINT32 port, char *tel);
+extern void fLib_Modem_waitcall(UINT32 port);
+extern int fLib_Modem_getchar(UINT32 port,int TIMEOUT);
+extern BOOL fLib_Modem_putchar(UINT32 port, INT8 Ch);
+//extern BOOL fLib_Modem_Initial(UINT32 port, int baudRate, UINT32 parity, UINT32 stopbit, UINT32 databit);
+//extern void fLib_Modem_close(UINT32 port);
+
+#endif
diff --git a/board/AndesTech/include/symbol.h b/board/AndesTech/include/symbol.h
new file mode 100644
index 0000000..51b22fe
--- /dev/null
+++ b/board/AndesTech/include/symbol.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2006 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/***************************************************************************
+* Copyright Faraday Technology Corp 2002-2003. All rights reserved. *
+*--------------------------------------------------------------------------*
+* Name:symbol.h *
+* Description: Faraday code library define *
+* Author: Fred Chien *
+* Date: 2002/03/01 *
+* Version:1.0 *
+*--------------------------------------------------------------------------*
+* Update by macpaul at andestech.com Andes Tech Crop. 2010 *
+****************************************************************************/
+
+#ifndef SYMBOL_H
+#define SYMBOL_H
+
+/* ASCII symbol define */
+
+#define CR 0x0D
+#define LF 0x0A
+#define BS 0x08
+#define ESC 27
+
+/* These defines are in a common coding practices header file */
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef NULL
+#define NULL 0
+#endif
+
+#ifndef ON
+#define ON 1
+#endif
+
+#ifndef OFF
+#define OFF 0
+#endif
+
+
+#ifndef ENABLE
+#define ENABLE 1
+#endif
+
+#ifndef DISABLE
+#define DISABLE 0
+#endif
+
+#ifndef PARITY_NONE
+#define PARITY_NONE 0
+#endif
+
+#ifndef PARITY_ODD
+#define PARITY_ODD 1
+#endif
+
+#ifndef PARITY_EVEN
+#define PARITY_EVEN 2
+#endif
+
+#ifndef PARITY_MARK
+#define PARITY_MARK 3
+#endif
+
+#ifndef PARITY_SPACE
+#define PARITY_SPACE 4
+#endif
+
+/* type define */
+typedef unsigned long long UINT64;
+typedef long long INT64;
+typedef unsigned int UINT32;
+typedef int INT32;
+typedef unsigned short UINT16;
+typedef short INT16;
+typedef unsigned char UINT8;
+typedef char INT8;
+typedef unsigned char BOOL;
+
+#endif
--
1.7.1
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