[U-Boot] [U-BOOT][PATCH 1/5] MX53: Add initial support for the Freescale MX53
Jason Liu
r64343 at freescale.com
Fri Jun 18 17:22:39 CEST 2010
The patch add initial support for the Freescale i.MX53 processor
(family arm cortex_a8).
Signed-off-by:Jason Liu <r64343 at freescale.com>
---
arch/arm/cpu/arm_cortexa8/mx53/Makefile | 48 +++
arch/arm/cpu/arm_cortexa8/mx53/clock.c | 458 ++++++++++++++++++++++++
arch/arm/cpu/arm_cortexa8/mx53/iomux.c | 151 ++++++++
arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S | 220 ++++++++++++
arch/arm/cpu/arm_cortexa8/mx53/soc.c | 93 +++++
arch/arm/cpu/arm_cortexa8/mx53/speed.c | 39 ++
arch/arm/cpu/arm_cortexa8/mx53/timer.c | 189 ++++++++++
arch/arm/cpu/arm_cortexa8/mx53/u-boot.lds | 62 ++++
arch/arm/include/asm/arch-mx53/clock.h | 51 +++
9 files changed, 1311 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm_cortexa8/mx53/Makefile b/arch/arm/cpu/arm_cortexa8/mx53/Makefile
new file mode 100644
index 0000000..7cfaa2c
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/mx53/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS = soc.o clock.o iomux.o timer.o speed.o
+SOBJS = lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm_cortexa8/mx53/clock.c b/arch/arm/cpu/arm_cortexa8/mx53/clock.c
new file mode 100644
index 0000000..93bcb20
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/mx53/clock.c
@@ -0,0 +1,458 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+
+enum pll_clocks {
+ PLL1_CLOCK = 0,
+ PLL2_CLOCK,
+ PLL3_CLOCK,
+ PLL4_CLOCK,
+ PLL_CLOCKS,
+};
+
+struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
+ [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
+ [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
+ [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
+ [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
+};
+
+struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+static u32 __decode_pll(struct mxc_pll_reg *pll, u32 infreq)
+{
+ u32 mfi, mfn, mfd, pd;
+
+ mfn = __raw_readl(&pll->mfn);
+ mfd = __raw_readl(&pll->mfd) + 1;
+ mfi = __raw_readl(&pll->op);
+ pd = (mfi & 0xF) + 1;
+ mfi = (mfi >> 4) & 0xF;
+ mfi = (mfi >= 5) ? mfi : 5;
+
+ return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
+}
+
+static u32 __get_mcu_main_clk(void)
+{
+ u32 reg, freq;
+ reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
+ MXC_CCM_CACRR_ARM_PODF_OFFSET;
+ freq = __decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX53_HCLK_FREQ);
+ return freq / (reg + 1);
+}
+
+static u32 __get_periph_clk(void)
+{
+ u32 reg;
+ reg = __raw_readl(&mxc_ccm->cbcdr);
+ if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
+ return __decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX53_HCLK_FREQ);
+
+ reg = __raw_readl(&mxc_ccm->cbcmr);
+ switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
+ MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+ case 0:
+ return __decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX53_HCLK_FREQ);
+ case 1:
+ return __decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX53_HCLK_FREQ);
+ default:
+ return 0;
+ }
+ /* NOTREACHED */
+}
+
+static u32 __get_ipg_clk(void)
+{
+ u32 ahb_podf, ipg_podf;
+
+ ahb_podf = __raw_readl(&mxc_ccm->cbcdr);
+ ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
+ MXC_CCM_CBCDR_IPG_PODF_OFFSET;
+ ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
+ MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+ return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
+}
+
+static u32 __get_ipg_per_clk(void)
+{
+ u32 pred1, pred2, podf;
+ if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
+ return __get_ipg_clk();
+ /* Fixme: not handle what about lpm */
+ podf = __raw_readl(&mxc_ccm->cbcdr);
+ pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
+ pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
+ podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
+
+ return __get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
+}
+
+static u32 __get_lp_apm(void)
+{
+ u32 ret_val = 0;
+ u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+
+ if (((ccsr >> MXC_CCM_CCSR_LP_APM_SEL_OFFSET) & 1) == 0)
+ ret_val = CONFIG_MX53_HCLK_FREQ;
+ else
+ ret_val = ((32768 * 1024));
+
+ return ret_val;
+}
+
+static u32 __get_uart_clk(void)
+{
+ u32 freq = 0, reg, pred, podf;
+ reg = __raw_readl(&mxc_ccm->cscmr1);
+ switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
+ MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
+ case 0x0:
+ freq = __decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX53_HCLK_FREQ);
+ break;
+ case 0x1:
+ freq = __decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX53_HCLK_FREQ);
+ break;
+ case 0x2:
+ freq = __decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX53_HCLK_FREQ);
+ break;
+ case 0x3:
+ freq = __get_lp_apm();
+ break;
+ default:
+ break;
+ }
+
+ reg = __raw_readl(&mxc_ccm->cscdr1);
+
+ pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
+
+ podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+ freq /= (pred + 1) * (podf + 1);
+
+ return freq;
+}
+
+
+static u32 __get_cspi_clk(void)
+{
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel, div;
+ u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
+ u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
+
+ pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
+ >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
+ pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
+ >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
+ clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
+ >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+
+ div = (pre_pdf + 1) * (pdf + 1);
+
+ switch (clk_sel) {
+ case 0:
+ ret_val = __decode_pll(mxc_plls[PLL1_CLOCK],
+ CONFIG_MX53_HCLK_FREQ) / div;
+ break;
+ case 1:
+ ret_val = __decode_pll(mxc_plls[PLL2_CLOCK],
+ CONFIG_MX53_HCLK_FREQ) / div;
+ break;
+ case 2:
+ ret_val = __decode_pll(mxc_plls[PLL3_CLOCK],
+ CONFIG_MX53_HCLK_FREQ) / div;
+ break;
+ default:
+ ret_val = __get_lp_apm() / div;
+ break;
+ }
+
+ return ret_val;
+}
+
+static u32 __get_axi_a_clk(void)
+{
+ u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+ u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
+ >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
+
+ return __get_periph_clk() / (pdf + 1);
+}
+
+static u32 __get_axi_b_clk(void)
+{
+ u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+ u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
+ >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
+
+ return __get_periph_clk() / (pdf + 1);
+}
+
+static u32 __get_ahb_clk(void)
+{
+ u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+ u32 pdf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \
+ >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+
+ return __get_periph_clk() / (pdf + 1);
+}
+
+
+static u32 __get_emi_slow_clk(void)
+{
+ u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+ u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
+ u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
+ >> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+
+ if (emi_clk_sel)
+ return __get_ahb_clk() / (pdf + 1);
+
+ return __get_periph_clk() / (pdf + 1);
+}
+
+static u32 __get_ddr_clk(void)
+{
+ u32 ret_val = 0;
+ u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
+ u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
+ >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+
+ switch (ddr_clk_sel) {
+ case 0:
+ ret_val = __get_axi_a_clk();
+ break;
+ case 1:
+ ret_val = __get_axi_b_clk();
+ break;
+ case 2:
+ ret_val = __get_emi_slow_clk();
+ break;
+ case 3:
+ ret_val = __get_ahb_clk();
+ break;
+ default:
+ break;
+ }
+
+ return ret_val;
+}
+
+static u32 __get_esdhc1_clk(void)
+{
+ u32 ret_val = 0, div, pre_pdf, pdf;
+ u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
+ u32 cscdr1 = __raw_readl(&mxc_ccm->cscdr1);
+ u32 esdh1_clk_sel;
+
+ esdh1_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK) \
+ >> MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
+ pre_pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) \
+ >> MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET;
+ pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) \
+ >> MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET ;
+
+ div = (pre_pdf + 1) * (pdf + 1);
+
+ switch (esdh1_clk_sel) {
+ case 0:
+ ret_val = __decode_pll(mxc_plls[PLL1_CLOCK],
+ CONFIG_MX53_HCLK_FREQ);
+ break;
+ case 1:
+ ret_val = __decode_pll(mxc_plls[PLL2_CLOCK],
+ CONFIG_MX53_HCLK_FREQ);
+ break;
+ case 2:
+ ret_val = __decode_pll(mxc_plls[PLL3_CLOCK],
+ CONFIG_MX53_HCLK_FREQ);
+ break;
+ case 3:
+ ret_val = __get_lp_apm();
+ break;
+ default:
+ break;
+ }
+
+ ret_val /= div;
+
+ return ret_val;
+}
+
+static u32 __get_esdhc3_clk(void)
+{
+ u32 ret_val = 0, div, pre_pdf, pdf;
+ u32 esdh3_clk_sel;
+ u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
+ u32 cscdr1 = __raw_readl(&mxc_ccm->cscdr1);
+ esdh3_clk_sel = (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK) \
+ >> MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET;
+ pre_pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK) \
+ >> MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET;
+ pdf = (cscdr1 & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK) \
+ >> MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET ;
+
+ div = (pre_pdf + 1) * (pdf + 1);
+
+ switch (esdh3_clk_sel) {
+ case 0:
+ ret_val = __decode_pll(mxc_plls[PLL1_CLOCK],
+ CONFIG_MX53_HCLK_FREQ);
+ break;
+ case 1:
+ ret_val = __decode_pll(mxc_plls[PLL2_CLOCK],
+ CONFIG_MX53_HCLK_FREQ);
+ break;
+ case 2:
+ ret_val = __decode_pll(mxc_plls[PLL3_CLOCK],
+ CONFIG_MX53_HCLK_FREQ);
+ break;
+ case 3:
+ ret_val = __get_lp_apm();
+ break;
+ default:
+ break;
+ }
+
+ ret_val /= div;
+
+ return ret_val;
+}
+
+static u32 __get_esdhc2_clk(void)
+{
+ u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
+ u32 esdh2_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ESDHC2_CLK_SEL;
+ if (esdh2_clk_sel)
+ return __get_esdhc3_clk();
+
+ return __get_esdhc1_clk();
+}
+
+static u32 __get_esdhc4_clk(void)
+{
+ u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
+ u32 esdh4_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ if (esdh4_clk_sel)
+ return __get_esdhc3_clk();
+
+ return __get_esdhc1_clk();
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return __get_mcu_main_clk();
+ case MXC_PER_CLK:
+ return __get_periph_clk();
+ case MXC_AHB_CLK:
+ return __get_ahb_clk();
+ case MXC_IPG_CLK:
+ return __get_ipg_clk();
+ case MXC_IPG_PERCLK:
+ return __get_ipg_per_clk();
+ case MXC_UART_CLK:
+ return __get_uart_clk();
+ case MXC_CSPI_CLK:
+ return __get_cspi_clk();
+ case MXC_AXI_A_CLK:
+ return __get_axi_a_clk();
+ case MXC_AXI_B_CLK:
+ return __get_axi_b_clk();
+ case MXC_EMI_SLOW_CLK:
+ return __get_emi_slow_clk();
+ case MXC_DDR_CLK:
+ return __get_ddr_clk();
+ case MXC_ESDHC_CLK:
+ return __get_esdhc1_clk();
+ case MXC_ESDHC2_CLK:
+ return __get_esdhc2_clk();
+ case MXC_ESDHC3_CLK:
+ return __get_esdhc3_clk();
+ case MXC_ESDHC4_CLK:
+ return __get_esdhc4_clk();
+ default:
+ break;
+ }
+ return -1;
+}
+
+u32 imx_get_uartclk(void)
+{
+ return mxc_get_clock(MXC_UART_CLK);
+}
+
+u32 imx_get_fecclk(void)
+{
+ return mxc_get_clock(MXC_IPG_CLK);
+
+}
+
+/*
+ * Dump some core clockes.
+ */
+int do_mx53_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ u32 freq;
+ freq = __decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX53_HCLK_FREQ);
+ printf("mx53 pll1: %dMHz\n", freq / 1000000);
+ freq = __decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX53_HCLK_FREQ);
+ printf("mx53 pll2: %dMHz\n", freq / 1000000);
+ freq = __decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX53_HCLK_FREQ);
+ printf("mx53 pll3: %dMHz\n", freq / 1000000);
+ printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
+ printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
+ printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
+ printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK));
+ printf("ahb clock : %dHz\n", mxc_get_clock(MXC_AHB_CLK));
+ printf("axi_a clock : %dHz\n", mxc_get_clock(MXC_AXI_A_CLK));
+ printf("axi_b clock : %dHz\n", mxc_get_clock(MXC_AXI_B_CLK));
+ printf("emi_slow clock: %dHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK));
+ printf("ddr clock : %dHz\n", mxc_get_clock(MXC_DDR_CLK));
+ printf("esdhc1 clock : %dHz\n", mxc_get_clock(MXC_ESDHC_CLK));
+ printf("esdhc2 clock : %dHz\n", mxc_get_clock(MXC_ESDHC2_CLK));
+ printf("esdhc3 clock : %dHz\n", mxc_get_clock(MXC_ESDHC3_CLK));
+ printf("esdhc4 clock : %dHz\n", mxc_get_clock(MXC_ESDHC4_CLK));
+
+ return 0;
+}
+
+/************************************************************************/
+
+U_BOOT_CMD(
+ clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx53_showclocks,
+ "display mx53 clocks\n",
+ ""
+);
diff --git a/arch/arm/cpu/arm_cortexa8/mx53/iomux.c b/arch/arm/cpu/arm_cortexa8/mx53/iomux.c
new file mode 100644
index 0000000..a5d9bbe
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/mx53/iomux.c
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx53_pins.h>
+#include <asm/arch/iomux.h>
+
+/* IOMUX register (base) addresses */
+enum iomux_reg_addr {
+ IOMUXGPR0 = IOMUXC_BASE_ADDR,
+ IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
+ IOMUXGPR2 = IOMUXC_BASE_ADDR + 0x008,
+ IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
+ IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
+ IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
+ IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
+};
+
+/* Get the iomux register address of this pin */
+static inline u32 _get_mux_reg(iomux_pin_name_t pin)
+{
+ u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
+
+ mux_reg += IOMUXSW_MUX_CTL;
+
+ return mux_reg;
+}
+
+/* Get the pad register address of this pin */
+static inline u32 _get_pad_reg(iomux_pin_name_t pin)
+{
+ u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
+
+ pad_reg += IOMUXSW_PAD_CTL;
+
+ return pad_reg;
+}
+
+/* Get the last iomux register address */
+static inline u32 _get_mux_end(void)
+{
+ return IOMUXSW_MUX_END;
+}
+
+/*
+ * This function is used to configure a pin through the IOMUX module.
+ * @param pin a pin number as defined in iomux_pin_name_t
+ * @param cfg an output function as defined in iomux_pin_cfg_t
+ *
+ * @return 0 if successful; Non-zero otherwise
+ */
+static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+ u32 mux_reg = _get_mux_reg(pin);
+
+ if ((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
+ return -1;
+ if (cfg == IOMUX_CONFIG_GPIO)
+ writel(PIN_TO_ALT_GPIO(pin), mux_reg);
+ else
+ writel(cfg, mux_reg);
+
+ return 0;
+}
+
+/*
+ * Request ownership for an IO pin. This function has to be the first one
+ * being called before that pin is used. The caller has to check the
+ * return value to make sure it returns 0.
+ *
+ * @param pin a name defined by iomux_pin_name_t
+ * @param cfg an input function as defined in iomux_pin_cfg_t
+ *
+ * @return 0 if successful; Non-zero otherwise
+ */
+int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+ int ret = iomux_config_mux(pin, cfg);
+
+ return ret;
+}
+
+/*
+ * Release ownership for an IO pin
+ *
+ * @param pin a name defined by iomux_pin_name_t
+ * @param cfg an input function as defined in iomux_pin_cfg_t
+ */
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+}
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in iomux_pin_name_t
+ * @param config value of elements defined in iomux_pad_config_t
+ */
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
+{
+ u32 pad_reg = _get_pad_reg(pin);
+
+ writel(config, pad_reg);
+}
+
+/*
+ * This function fetches the pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in iomux_pin_name_t
+ *
+ * @return pad config value of the request pin
+ */
+unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
+{
+ u32 pad_reg = _get_pad_reg(pin);
+
+ return readl(pad_reg);
+}
+
+/*
+ * This function configures input path.
+ *
+ * @param input index of input select register
+ * @param config the binary value of elements
+ */
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
+{
+ u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
+
+ writel(config, reg);
+}
diff --git a/arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S b/arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S
new file mode 100644
index 0000000..e32ec86
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/mx53/lowlevel_init.S
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg at denx.de>
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/asm-offsets.h>
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+ /* explicitly disable L2 cache */
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #0x2
+ mcr 15, 0, r0, c1, c0, 1
+
+ /* reconfigure L2 cache aux control reg */
+ mov r0, #0xC0 /* tag RAM */
+ add r0, r0, #0x4 /* data RAM */
+ orr r0, r0, #(1 << 24) /* disable write allocate delay */
+ orr r0, r0, #(1 << 23) /* disable write allocate combine */
+ orr r0, r0, #(1 << 22) /* disable write allocate */
+
+ mcr 15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =0x77777777
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+ ldr r0, =\pll
+ ldr r1, =0x00001232
+ str r1, [r0, #PLL_DP_CTL]
+ mov r1, #0x2
+ str r1, [r0, #PLL_DP_CONFIG]
+
+ ldr r1, W_DP_OP_\freq
+ str r1, [r0, #PLL_DP_OP]
+ str r1, [r0, #PLL_DP_HFS_OP]
+
+ ldr r1, W_DP_MFD_\freq
+ str r1, [r0, #PLL_DP_MFD]
+ str r1, [r0, #PLL_DP_HFS_MFD]
+
+ ldr r1, W_DP_MFN_\freq
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+ ldr r1, =0x00001232
+ str r1, [r0, #PLL_DP_CTL]
+1: ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+.endm
+
+.macro init_clock
+ ldr r0, CCM_BASE_ADDR_W
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+
+ setup_pll PLL1_BASE_ADDR, 800
+
+ setup_pll PLL3_BASE_ADDR, 400
+
+ /* Switch peripheral to PLL3 */
+ ldr r0, CCM_BASE_ADDR_W
+ ldr r1, CCM_VAL_0x00015154
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, CCM_VAL_0x02888945
+ orr r1, r1, #(1 << 16)
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure change is effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ
+
+ /* Switch peripheral to PLL2 */
+ ldr r0, CCM_BASE_ADDR_W
+ ldr r1, CCM_VAL_0x00808145
+ orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
+ orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
+ orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ ldr r1, CCM_VAL_0x00016154
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ /* make sure change is effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ setup_pll PLL3_BASE_ADDR, 216
+
+ /* Set the platform clock dividers */
+ ldr r0, PLATFORM_BASE_ADDR_W
+ ldr r1, PLATFORM_CLOCK_DIV_W
+ str r1, [r0, #PLATFORM_ICGC]
+
+ ldr r0, CCM_BASE_ADDR_W
+ mov r1, #1
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1. */
+ mov r1, #0x0
+ str r1, [r0, #CLKCTL_CCSR]
+
+ ldr r1, [r0, #CLKCTL_CSCDR1]
+ orr r1, r1, #0x3f
+ eor r1, r1, #0x3f
+ orr r1, r1, #0x21
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+ str r1, [r0, #CLKCTL_CCGR7]
+
+ mov r1, #0x00000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* for cko - for ARM div by 8 */
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+#ifdef ENABLE_IMPRECISE_ABORT
+ mrs r1, spsr /* save old spsr */
+ mrs r0, cpsr /* read out the cpsr */
+ bic r0, r0, #0x100 /* clear the A bit */
+ msr spsr, r0 /* update spsr */
+ add lr, pc, #0x8 /* update lr */
+ movs pc, lr /* update cpsr */
+ nop
+ nop
+ nop
+ nop
+ msr spsr, r1 /* restore old spsr */
+#endif
+
+ /* ARM errata ID #468414 */
+ mrc 15, 0, r1, c1, c0, 1
+ orr r1, r1, #(1 << 5) /* enable L1NEON bit */
+ mcr 15, 0, r1, c1, c0, 1
+
+ init_l2cc
+
+ init_aips
+
+ init_clock
+
+ mov pc, lr
+
+/* Board level setting value */
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+CCM_VAL_0x00016154: .word 0x00016154
+CCM_VAL_0x00808145: .word 0x00808145
+CCM_VAL_0x00015154: .word 0x00015154
+CCM_VAL_0x02888945: .word 0x02888945
+W_DP_OP_800: .word DP_OP_800
+W_DP_MFD_800: .word DP_MFD_800
+W_DP_MFN_800: .word DP_MFN_800
+W_DP_OP_600: .word DP_OP_600
+W_DP_MFD_600: .word DP_MFD_600
+W_DP_MFN_600: .word DP_MFN_600
+W_DP_OP_400: .word DP_OP_400
+W_DP_MFD_400: .word DP_MFD_400
+W_DP_MFN_400: .word DP_MFN_400
+W_DP_OP_216: .word DP_OP_216
+W_DP_MFD_216: .word DP_MFD_216
+W_DP_MFN_216: .word DP_MFN_216
+PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W: .word 0x00000124
diff --git a/arch/arm/cpu/arm_cortexa8/mx53/soc.c b/arch/arm/cpu/arm_cortexa8/mx53/soc.c
new file mode 100644
index 0000000..58c4998
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/mx53/soc.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
+u32 get_cpu_rev(void)
+{
+ int system_rev;
+
+ system_rev = 0x53000 | CHIP_REV_1_0;
+
+ return system_rev;
+}
+
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+ printf("CPU: Freescale i.MX53 family rev%d.%d at %d MHz\n",
+ (cpurev & 0xF0) >> 4,
+ (cpurev & 0x0F) >> 4,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ return 0;
+}
+#endif
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+#if defined(CONFIG_FEC_MXC)
+extern int fecmxc_initialize(bd_t *bis);
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+ rc = fecmxc_initialize(bis);
+#endif
+
+ return rc;
+}
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_ESDHC
+ return fsl_esdhc_mmc_init(bis);
+#else
+ return 0;
+#endif
+}
+
+
+void reset_cpu(ulong addr)
+{
+ __raw_writew(4, WDOG1_BASE_ADDR);
+}
diff --git a/arch/arm/cpu/arm_cortexa8/mx53/speed.c b/arch/arm/cpu/arm_cortexa8/mx53/speed.c
new file mode 100644
index 0000000..8d8f6ba
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/mx53/speed.c
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+int get_clocks(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+ return 0;
+}
diff --git a/arch/arm/cpu/arm_cortexa8/mx53/timer.c b/arch/arm/cpu/arm_cortexa8/mx53/timer.c
new file mode 100644
index 0000000..c1ef1ad
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/mx53/timer.c
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <div64.h>
+
+/* General purpose timers registers */
+struct mxc_gpt {
+ unsigned int control;
+ unsigned int prescaler;
+ unsigned int status;
+ unsigned int nouse[6];
+ unsigned int counter;
+};
+
+static struct mxc_gpt *gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR (1<<15) /* Software reset */
+#define GPTCR_FRR (1<<9) /* Freerun / restart */
+#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
+#define GPTCR_TEN (1) /* Timer enable */
+
+static ulong timestamp;
+static ulong lastinc;
+
+/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
+#ifdef CONFIG_MX53_TIMER_HIGH_PRECISION
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, CONFIG_MX53_CLK32);
+ return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+ time *= CONFIG_MX53_CLK32;
+ do_div(time, CONFIG_SYS_HZ);
+ return time;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+ us = us * CONFIG_MX53_CLK32 + 999999;
+ do_div(us, 1000000);
+ return us;
+}
+#else
+/* ~2% error */
+#define TICK_PER_TIME ((CONFIG_MX53_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK (1000000 / CONFIG_MX53_CLK32)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ do_div(tick, TICK_PER_TIME);
+ return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+ return time * TICK_PER_TIME;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+ us += US_PER_TICK - 1;
+ do_div(us, US_PER_TICK);
+ return us;
+}
+#endif
+
+/* The 32768Hz 32-bit timer overruns in 131072 seconds */
+int timer_init (void)
+{
+ int i, reg;
+
+ /* setup GP Timer 1 */
+ __raw_writel(GPTCR_SWR, &gpt->control);
+
+ /* We have no udelay by now */
+ for (i = 0; i < 100; i++)
+ __raw_writel(0, &gpt->control);
+
+ /* prescaler = 1 */
+ __raw_writel(0, &gpt->prescaler);
+
+ /* Freerun Mode, PERCLK1 input */
+ reg = __raw_readl(&gpt->control);
+ __raw_writel(reg | GPTCR_CLKSOURCE_32 | GPTCR_FRR, &gpt->control);
+
+ reg = __raw_readl(&gpt->control);
+ __raw_writel(reg | GPTCR_TEN, &gpt->control);
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+void reset_timer_masked (void)
+{
+ /* capture current incrementer value time */
+ lastinc = __raw_readl(&gpt->counter);
+
+ /* start "advancing" time stamp from 0 */
+ timestamp = 0;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+unsigned long long get_ticks (void)
+{
+ /* current tick value */
+ ulong now = __raw_readl(&gpt->counter);
+
+ if (now >= lastinc) {
+ /*
+ * normal mode (non roll)
+ * move stamp forward with absolut diff ticks
+ */
+ timestamp += (now - lastinc);
+ } else {
+ /* we have rollover of incrementer */
+ timestamp += (0xFFFFFFFF - lastinc) + now;
+ }
+ lastinc = now;
+
+ return timestamp;
+}
+
+ulong get_timer_masked (void)
+{
+ /*
+ * get_ticks() returns a long long (64 bit), it wraps in
+ * 2^64 / CONFIG_MX53_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+ * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+ * 5 * 10^6 days - long enough.
+ */
+ return tick_to_time(get_ticks());
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = time_to_tick(t);
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay (unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = us_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
+}
diff --git a/arch/arm/cpu/arm_cortexa8/mx53/u-boot.lds b/arch/arm/cpu/arm_cortexa8/mx53/u-boot.lds
new file mode 100644
index 0000000..6a674d9
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/mx53/u-boot.lds
@@ -0,0 +1,62 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+ *
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ board/freescale/mx53evk/flash_header.o
+ arch/arm/cpu/arm_cortexa8/start.o
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/arch/arm/include/asm/arch-mx53/clock.h b/arch/arm/include/asm/arch-mx53/clock.h
new file mode 100644
index 0000000..e986462
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx53/clock.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_PER_CLK,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_IPG_PERCLK,
+ MXC_UART_CLK,
+ MXC_CSPI_CLK,
+ MXC_AXI_A_CLK,
+ MXC_AXI_B_CLK,
+ MXC_EMI_SLOW_CLK,
+ MXC_DDR_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_ESDHC4_CLK,
+};
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+
+unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_CLOCK_H */
--
1.7.0.4
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