[U-Boot] FSL UPM NAND read not proper from u-boot

[lloyd vas]

Hi,

  Our development board using MPC8321E processor have two FLASH memory
devices, one connected in GPCM (NOR Flash) and
another connected in UPM mode(NAND Flash is STM Micro electronics chip
NAND512W3A2C). I understood from the mailing list user discussions,
 that to support it in u-boot 1.3.2 code base I can port code changes
similar to MPC836x RDK code base from u-boot 1.3.4 code base.
Considering this I had merged the code changes of MPC836x RDK support, apart
from files (drivers/mtd/nand/fsl_upm.c and
board/freescale/mpc8323erdb/nand.c),
below summary changes were made

1) GPIO port configured is as below

File: board/freescale/mpc8323erdb/mpc8323erdb.c


const qe_iop_conf_t qe_iop_conf_tab[] = {
    /* UCC3 */

#ifdef FSL_NAND_SUPPORT
    /* NAND device connected to  PORT C 15th PIN */
    {2, 15, 2, 0, 0}, /* NAND_RYnBY */
#endif
}

2) To configure 8-bit port size (64MB NAND Flash) and using UPM A
configuration

File: include/configs/MPC8323ERDB.h


// NOR Flash configuration starts here 16MB (16-bit)
#define CFG_FLASH_BASE      0xFE000000  /* FLASH base address */

#define CFG_LBLAWBAR0_PRELIM    CFG_FLASH_BASE  /* Window base at flash base
*/
#define CFG_LBLAWAR0_PRELIM    (LBLAWAR_EN | LBLAWAR_16MB)/* 16MB window
size */
#define CFG_BR0_PRELIM  (CFG_FLASH_BASE |   /* Flash Base address */ \
            (2 << BR_PS_SHIFT) |    /* 16 bit port size */ \
            BR_V)           /* valid */

#define CFG_LBLAWBAR1_PRELIM    CFG_NAND_BASE
#define CFG_LBLAWAR1_PRELIM    (LBLAWAR_EN | LBLAWAR_64MB)/* 64MB window
size */

// NOR Flash configuration ends here

//NAND Flash configuration starts here - 64MB (8bit)
#define CFG_NAND_BASE       0xf8000000
/* Port size 8 bit, UPMA */
#define CFG_BR1_PRELIM      (CFG_NAND_BASE |\
                             BR_PS_8|  /* 8 bit Port size */\
                             BR_MS_UPMA | /* UPMA */\
                             BR_V)

#define CFG_OR1_PRELIM       (OR_AM_64MB | /* 64MB */\
                              0x00006000 |  /* Reserved set ??? */\
                              OR_UPM_BI | /* bank does not support accesses
*/\
                              OR_UPM_EAD) /* Extra bus clock cycles added */


#ifdef FSL_NAND_SUPPORT
/* NAND: cache-inhibit and guarded */
#define CFG_IBAT3L  (CFG_NAND_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT3U  (CFG_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
#define CFG_DBAT3L  CFG_IBAT3L
#define CFG_DBAT3U  CFG_IBAT3U
#endif // FSL_NAND_SUPPORT
//NAND Flash configuration ends here

//LCRR
#define CFG_LCRR        (LCRR_DBYP | LCRR_EADC_3 | LCRR_CLKDIV_2)


3)
Using the UPM editor tool provided by freescale I had generated the below
UPM RAM in the file board/freescale/mpc8323erdb/nand.c
static const u32 upm_array[] = {

  0x0ff03c00,  0x0ff03c00,  0x0ff03c04,  0x0ff33c00, //Words 0 to 3
    0xfff33c01,  0xfffffc30,  0xfffffc30,  0xfffffc30, //Words 4 to 7
    0x0faf3c30,  0x0faf3c30,  0x0faf3c30,  0x0fff3c34, //Words 8 to 11
    0xffff3c31,  0xfffffc30,  0xfffffc30,  0xfffffc30, //Words 12 to 15
    0x0fa3fc30,  0x0fa3fc30,  0x0fa3fc30,  0x0ff3fc34, //Words 16 to 19
    0xfff3fc31,  0xfffffc30,  0xfffffc30,  0xfffffc30, //Words 20 to 23
    0x0ff33c00,  0x0fa33c00,  0x0fa33c04,  0x0ff33c00, //Words 24 to 27
    0xfff33c01,  0xfff0fc30,  0xfff0fc30,  0xfff0fc30, //Words 28 to 31
    0xfff3fc30,  0xfff3fc30,  0xfff6fc30,  0xfffcfc30, //Words 32 to 35
    0xfffcfc30,  0xfffcfc30,  0xfffcfc30,  0xfffcfc30, //Words 36 to 39
    0xfffcfc30,  0xfffcfc30,  0xfffcfc30,  0xfffcfc30, //Words 40 to 43
    0xfffdfc30,  0xfffffc30,  0xfffffc30,  0xfffffc31, //Words 44 to 47
    0xfffffc30,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 48 to 51
    0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 52 to 55
    0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, //Words 56 to 59
    0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01  //Words 60 to 63

}

Am I missing out any other changes?

I have the following observation to be shared on the debugging this
development board

1) UPM RAM Array intialization is succesfull ( I verified using the UPM RAM
array read command)

2) For the memory mapped region of NAND u-boot memory display using the
command  "md" shows the values like 4040, 8080, 3f3f,7f7f and ffff. Is it
showing some junk values?

3) Intially probing of the nand using nand_scan() says "No NAND device
found", I meant manufacture ID and device ID is displayed as zero.
But, we just want to know whether the sequence followed for reading the IDs
of device and manufacture is the proper provided in fsl_upm.c for our NAND
flash device.
NAND flash datasheet link is (
http://www.alldatasheet.com/datasheet-pdf/pdf/228090/NUMONYX/NAND512R3A2C.html
).

4)  Another thing I observed in the nand_scan() during the READ device and
manufacturer ID that we are executing the run pattern for writing the
command and address location. But, it looks like we are not executing the
UPM run pattern for reading the data( device ID and manufacturer ID) in the
process.

Thanks in advance.

Regards,
Lloyd