[U-Boot] [PATCH v2 6/7] mpc5121: add support for PDM360NG board
Anatolij Gustschin
agust at denx.de
Tue Mar 16 17:10:07 CET 2010
PDM360NG is a MPC5121E based board by ifm ecomatic gmbh.
Signed-off-by: Michael Weiss <michael.weiss at ifm.com>
Signed-off-by: Anatolij Gustschin <agust at denx.de>
---
Changes since first version:
- don't include RLE8 bitmap support in DIU code,
now it is in common code submitted to U-Boot ML
as separate patch. It is also extended to support
more video formats.
- fixed e-mail format
- keep the list of targets sorted in the Makefile
- move POST code into separate file
- move post_word_load/store code to common file for
all mpc512x boards
- create a file with common board config options
for mpc512x boards which can be included in the
board config file.
- use cfb_console driver for frame buffer support
- allow configuration of coprocessor communication
parameters (baudrate, wait delay) in the board config
file
MAKEALL | 1 +
Makefile | 3 +
board/freescale/common/fsl_diu_fb.c | 29 ++-
board/pdm360ng/Makefile | 52 ++++
board/pdm360ng/config.mk | 24 ++
board/pdm360ng/pdm360ng.c | 525 +++++++++++++++++++++++++++++++++++
board/pdm360ng/post.c | 75 +++++
cpu/mpc512x/diu.c | 14 +-
include/configs/mpc5121-common.h | 52 ++++
include/configs/pdm360ng.h | 520 ++++++++++++++++++++++++++++++++++
include/post.h | 1 +
post/tests.c | 4 +
12 files changed, 1294 insertions(+), 6 deletions(-)
create mode 100644 board/pdm360ng/Makefile
create mode 100644 board/pdm360ng/config.mk
create mode 100644 board/pdm360ng/pdm360ng.c
create mode 100644 board/pdm360ng/post.c
create mode 100644 include/configs/mpc5121-common.h
create mode 100644 include/configs/pdm360ng.h
diff --git a/MAKEALL b/MAKEALL
index beacb5f..deda7e1 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -93,6 +93,7 @@ LIST_512x=" \
aria \
mecp5123 \
mpc5121ads \
+ pdm360ng \
"
#########################################################################
diff --git a/Makefile b/Makefile
index d801e25..1068e6a 100644
--- a/Makefile
+++ b/Makefile
@@ -828,6 +828,9 @@ mpc5121ads_rev2_config \
fi
@$(MKCONFIG) -a mpc5121ads ppc mpc512x mpc5121ads freescale
+pdm360ng_config: unconfig
+ @$(MKCONFIG) -a pdm360ng ppc mpc512x pdm360ng
+
#########################################################################
## MPC8xx Systems
#########################################################################
diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c
index 2fc878b..ae5e7a7 100644
--- a/board/freescale/common/fsl_diu_fb.c
+++ b/board/freescale/common/fsl_diu_fb.c
@@ -50,6 +50,22 @@ struct fb_videomode {
#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
+/* This setting is used for the ifm pdm360ng with PRIMEVIEW PM070WL3 */
+static struct fb_videomode fsl_diu_mode_800 = {
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 31250,
+ .left_margin = 86,
+ .right_margin = 42,
+ .upper_margin = 33,
+ .lower_margin = 10,
+ .hsync_len = 128,
+ .vsync_len = 2,
+ .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
/*
* These parameters give default parameters
* for video output 1024x768,
@@ -210,9 +226,14 @@ int fsl_diu_init(int xres,
disable_lcdc();
- if (xres == 1280) {
+ switch (xres) {
+ case 800:
+ fsl_diu_mode_db = &fsl_diu_mode_800;
+ break;
+ case 1280:
fsl_diu_mode_db = &fsl_diu_mode_1280;
- } else {
+ break;
+ default:
fsl_diu_mode_db = &fsl_diu_mode_1024;
}
@@ -519,9 +540,9 @@ int fsl_diu_display_bmp(unsigned char *bmp,
b = *bitmap++;
for (k = 0; k < 8; k++) {
if (b & 0x80)
- *fb_t = palette[1];
+ *fb_t++ = palette[1];
else
- *fb_t = palette[0];
+ *fb_t++ = palette[0];
b = b << 1;
}
}
diff --git a/board/pdm360ng/Makefile b/board/pdm360ng/Makefile
new file mode 100644
index 0000000..113ac0a
--- /dev/null
+++ b/board/pdm360ng/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_HAS_POST) += post.o
+
+COBJS := $(COBJS-y)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/pdm360ng/config.mk b/board/pdm360ng/config.mk
new file mode 100644
index 0000000..56337e4
--- /dev/null
+++ b/board/pdm360ng/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2009
+# Michael Weiß, ifm ecomatic gmbh, michael.weiss at ifm.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xF0000000
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
new file mode 100644
index 0000000..ed95eb4
--- /dev/null
+++ b/board/pdm360ng/pdm360ng.c
@@ -0,0 +1,525 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd at denx.de>
+ *
+ * (C) Copyright 2009
+ * Michael Weiß, ifm ecomatic gmbh, michael.weiss at ifm.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+#include <serial.h>
+#include <post.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
+ CLOCK_SCCR1_LPC_EN | \
+ CLOCK_SCCR1_NFC_EN | \
+ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
+ CLOCK_SCCR1_PSCFIFO_EN | \
+ CLOCK_SCCR1_DDR_EN | \
+ CLOCK_SCCR1_FEC_EN | \
+ CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
+ CLOCK_SCCR2_SPDIF_EN | \
+ CLOCK_SCCR2_DIU_EN | \
+ CLOCK_SCCR2_I2C_EN)
+
+int board_early_init_f(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ /*
+ * Initialize Local Window for FLASH-Bank1 access (CS1)
+ */
+ out_be32(&im->sysconf.lpcs1aw,
+ CSAW_START(CONFIG_SYS_FLASH1_BASE) |
+ CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH1_SIZE)
+ );
+ out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
+
+ /*
+ * Local Window for MRAM access (CS2)
+ */
+ out_be32(&im->sysconf.lpcs2aw,
+ CSAW_START(CONFIG_SYS_MRAM_BASE) |
+ CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE)
+ );
+ out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+
+ sync_law(&im->sysconf.lpcs2aw);
+
+ /*
+ * Configure Flash Speed
+ */
+ out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+ out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
+ /*
+ * Enable clocks
+ */
+ out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+ out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+ setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
+
+ return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+ u32 pdm360ng_init_seq[] = {
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_MICRON_INIT_DEV_OP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_EM2,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_EM2,
+ CONFIG_SYS_DDRCMD_EM3,
+ CONFIG_SYS_DDRCMD_EN_DLL,
+ CONFIG_SYS_DDRCMD_RES_DLL,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_MICRON_INIT_DEV_OP,
+ CONFIG_SYS_DDRCMD_OCD_DEFAULT,
+ CONFIG_SYS_DDRCMD_OCD_EXIT,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_NOP
+ };
+
+ return fixed_sdram(NULL, pdm360ng_init_seq,
+ ARRAY_SIZE(pdm360ng_init_seq));
+}
+
+#if defined(CONFIG_SERIAL_MULTI)
+static int set_lcd_brightness(char *);
+#endif
+
+int misc_init_r(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+#ifdef CONFIG_FSL_DIU_FB
+# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
+ mpc5121_diu_init();
+#endif
+#if defined(CONFIG_SERIAL_MULTI)
+ set_lcd_brightness(0);
+#endif
+ /* Switch LCD-Backlight and LVDS-Interface on */
+ setbits_be32(&im->gpio.gpdir, 0x01040000);
+ clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
+#endif
+
+#if defined(CONFIG_HARD_I2C)
+ if (!getenv("ethaddr")) {
+ uchar buf[6];
+ char mac[18];
+ int ret;
+
+ /* I2C-0 for on-board eeprom */
+ i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
+
+ /* Read ethaddr from EEPROM */
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
+ if (!ret) {
+ sprintf(mac, "%02X:%02X:%02X:%02X:%02X:%02X",
+ buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ /* Owned by IFM ? */
+ if (strstr(mac, "00:02:01") != mac) {
+ printf("Illegal MAC address in EEPROM: %s\n",
+ mac);
+ } else {
+ debug("Using MAC from I2C EEPROM: %s\n", mac);
+ setenv("ethaddr", mac);
+ }
+ } else {
+ printf("Error: Unable to read MAC from I2C"
+ " EEPROM at address %02X:%02X\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
+ }
+ }
+#endif /* defined(CONFIG_HARD_I2C) */
+
+ return 0;
+}
+
+static iopin_t ioregs_init[] = {
+ /* FUNC1=LPC_CS4 */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
+ IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=CAN3_TX */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO12 Sets Next 5 to GPIO pads */
+ /* GPIO12-GPIO16 */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_ior), 5, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
+ /* DIU_LD22-DIU_LD23 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
+ /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
+ /* VIU_DATA0-VIU_DATA2 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=FEC_TXD_0 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
+ /* VIU_DATA3, VIU_DATA4 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
+ /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
+ /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
+ /* DIU_LD00-DIU_LD21 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
+ /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
+ {
+ offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC2=CAN3_RX */
+ {
+ offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* Sets lowest slew on 2 CAN_TX Pins*/
+ {
+ offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
+ /* CAN4_TX, CAN4_RX */
+ {
+ offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
+ /* GPIO8, GPIO9 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
+ /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
+ /* FEC_RXD_3, FEC_RXD_2 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=GPIO17 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
+ /* GPIO2, GPIO20, GPIO21 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC2=VIU_PIX_CLK */
+ {
+ offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
+ /* GPIO24, GPIO25 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC1=NFC_CE2 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
+ IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
+ /* VIU_DATA5-VIU_DATA9 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
+ /* LPC_TSIZ1-LPC_TSIZ2 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=LPC_TS */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=GPIO16 Sets Next 5 to GPIO pads */
+ /* GPIO16-GPIO19, GPT7/GPIO7 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc7_0), 5, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO20 Sets Next 2 to GPIO pads */
+ /* GPIO20, GPIO21 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc8_0), 2, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO0/GPT0 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
+ /* GPIO8, GPIO9 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc10_0), 2, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
+ /* GPIO2, GPIO12, GPIO13 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc10_4), 3, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC2=DIU_DE */
+ {
+ offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ }
+};
+
+int checkboard (void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ puts("Board: PDM360NG\n");
+
+ /* initialize function mux & slew rate IO inter alia on IO Pins */
+
+ iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+ /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
+ setbits_be32(&im->io_ctrl.io_control_gp, (1 << 0)); /* GP_MUX7->GPIO7 */
+
+ /* configure GPIO24 (VIU_CE), output/high */
+ setbits_be32(&im->gpio.gpdir, 0x80);
+ setbits_be32(&im->gpio.gpdat, 0x80);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+struct node_info nodes[] = {
+ { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
+ { "cfi-flash", MTD_DEV_TYPE_NOR, },
+};
+#endif
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_SERIAL_MULTI)
+/*
+ * If argument is NULL, set the LCD brightness to the
+ * value from "brightness" environment variable. Set
+ * the LCD brightness to the value specified by the
+ * argument otherwise. Default brightness is zero.
+ */
+#define MAX_BRIGHTNESS 99
+static int set_lcd_brightness(char *brightness)
+{
+ struct stdio_dev *cop_port;
+ char *env;
+ char cmd_buf[20];
+ int val = 0;
+ int cs = 0;
+ int len, i;
+
+ if (brightness) {
+ val = simple_strtol(brightness, NULL, 10);
+ } else {
+ env = getenv("brightness");
+ if (env)
+ val = simple_strtol(env, NULL, 10);
+ }
+
+ if (val < 0)
+ val = 0;
+
+ if (val > MAX_BRIGHTNESS)
+ val = MAX_BRIGHTNESS;
+
+ sprintf(cmd_buf, "$SB;%04d;", val);
+
+ len = strlen(cmd_buf);
+ for (i = 1; i <= len; i++)
+ cs += cmd_buf[i];
+
+ cs = (~cs + 1) & 0xff;
+ sprintf(cmd_buf + len, "%02X\n", cs);
+
+ /* IO Coprocessor communication */
+ cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
+ if (!cop_port) {
+ printf("Error: Can't open IO Coprocessor port.\n");
+ return -1;
+ }
+
+ debug("%s: cmd: %s", __func__, cmd_buf);
+ write_port(cop_port, cmd_buf);
+ /*
+ * Wait for transmission and maybe response data
+ * before closing the port.
+ */
+ udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
+ memset(cmd_buf, 0, sizeof(cmd_buf));
+ len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
+ if (len)
+ printf("Error: %s\n", cmd_buf);
+
+ close_port(4);
+
+ return 0;
+}
+
+static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
+ int argc, char *argv[])
+{
+ if (argc < 2) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ return set_lcd_brightness(argv[1]);
+}
+
+U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
+ "set LCD brightness",
+ "<brightness> - set LCD backlight level to <brightness>.\n"
+);
+#endif /* CONFIG_SERIAL_MULTI */
diff --git a/board/pdm360ng/post.c b/board/pdm360ng/post.c
new file mode 100644
index 0000000..8e47c5e
--- /dev/null
+++ b/board/pdm360ng/post.c
@@ -0,0 +1,75 @@
+/*
+ * Co-Processor communication POST
+ */
+
+#include <common.h>
+#include <post.h>
+#include <serial.h>
+
+#if defined(CONFIG_SERIAL_MULTI)
+
+/*
+ * Actually the termination sequence of the coprocessor
+ * commands is "\r\n" (CR LF), but here we use a side effect of
+ * the putc() routine of the serial driver which checks for LF
+ * and sends CR before sending LF. Therefore the termination
+ * sequence in the command below is only "\n".
+ * "alive" string is the coprocessor response for ping command
+ * and not a command, therefore it is terminated with "\r\n".
+ */
+char alive[] = "$AL;38\r\n";
+char ping[] = "$PI;2C\n";
+
+int pdm360ng_coprocessor_post_test(int flags)
+{
+ struct stdio_dev *cop_port;
+ int ret;
+ char buf[10];
+
+ /* Test IO Coprocessor communication */
+ cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
+ if (!cop_port)
+ return -1;
+
+ write_port(cop_port, ping);
+ udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
+
+ memset(buf, 0, sizeof(buf));
+ ret = read_port(cop_port, buf, sizeof(buf));
+ close_port(4);
+ if (ret <= 0) {
+ post_log("Error: Can't read IO Coprocessor port.\n");
+ return -1;
+ }
+
+ if (strcmp(buf, alive)) {
+ post_log("Error: IO-Cop. resp.: %s\n", buf);
+ return -1;
+ }
+
+ /* Test WD Coprocessor communication */
+ cop_port = open_port(1, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
+ if (!cop_port) {
+ post_log("Error: Can't open WD Coprocessor port.\n");
+ return -1;
+ }
+
+ write_port(cop_port, ping);
+ udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
+
+ memset(buf, 0, sizeof(buf));
+ ret = read_port(cop_port, buf, sizeof(buf));
+ close_port(1);
+ if (ret <= 0) {
+ post_log("Error: Can't read WD Coprocessor port.\n");
+ return -1;
+ }
+
+ if (strcmp(buf, alive)) {
+ post_log("Error: WD-Cop. resp.: %s\n", buf);
+ return -1;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_SERIAL_MULTI */
diff --git a/cpu/mpc512x/diu.c b/cpu/mpc512x/diu.c
index a24f395..fc43a9d 100644
--- a/cpu/mpc512x/diu.c
+++ b/cpu/mpc512x/diu.c
@@ -68,8 +68,13 @@ char *valid_bmp(char *addr)
unsigned long h_addr;
h_addr = simple_strtoul(addr, NULL, 16);
- if (h_addr < CONFIG_SYS_FLASH_BASE ||
- h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) {
+ if ((h_addr < CONFIG_SYS_FLASH_BASE ||
+ h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1))
+#if defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)
+ && (h_addr < CONFIG_SYS_FLASH1_BASE ||
+ h_addr >= (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_FLASH1_SIZE - 1))
+#endif
+ ) {
printf("bmp addr %lx is not a valid flash address\n", h_addr);
return 0;
} else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) {
@@ -85,8 +90,13 @@ int mpc5121_diu_init(void)
char *bmp = NULL;
char *bmp_env;
+#ifdef CONFIG_PDM360NG
+ xres = 800;
+ yres = 480;
+#else
xres = 1024;
yres = 768;
+#endif
pixel_format = 0x88883316;
debug("mpc5121_diu_init\n");
diff --git a/include/configs/mpc5121-common.h b/include/configs/mpc5121-common.h
new file mode 100644
index 0000000..2bc9041
--- /dev/null
+++ b/include/configs/mpc5121-common.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2010 DENX Software Engineering
+ * Anatolij Gustschin <agust at denx.de>
+ *
+ * Common configuration options for MPC5121 based boards
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MPC5121_COMMON_H
+#define __MPC5121_COMMON_H
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+
+/*
+ * Serial console
+ */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_CMDLINE_EDITING 1 /* command line history */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#endif /* __MPC5121_COMMON_H */
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
new file mode 100644
index 0000000..e0fd56b
--- /dev/null
+++ b/include/configs/pdm360ng.h
@@ -0,0 +1,520 @@
+/*
+ * (C) Copyright 2009
+ * Michael Weiß, ifm ecomatic gmbh, <michael.weiss at ifm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * pdm360ng board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+#define CONFIG_PDM360NG 1
+#define CONFIG_PDM360NG_BIG /* PDM360NG with big memory */
+#undef CONFIG_PDM360NG_SMALL /* PDM360NG with small memory */
+
+/*
+ * Memory map for the PDM360NG board:
+ *
+ * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB)
+ * 0x2000_0000 - 0x3FFF_FFFF reserved (DDR RAM (512 MB)
+ * 0x5000_0000 - 0x5001_FFFF SRAM (128 KB)
+ * 0x5004_0000 - 0x5005_FFFF MRAM (CS2) (128 KB)
+ * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
+ * 0xF000_0000 - 0xF7FF_FFFF NOR FLASH (CS0) (128 MB)
+ * 0xF800_0000 - 0xFFFF_FFFF NOR FLASH (CS1) (128 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC512X 1 /* MPC512X family */
+#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
+#undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */
+
+/* Used for silent command in environment */
+#define CONFIG_SYS_DEVICE_NULLDEV
+#define CONFIG_SILENT_CONSOLE
+
+/* Video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#endif
+
+#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR 0x80000000
+#define CONFIG_SYS_DIU_ADDR ((CONFIG_SYS_IMMR) + 0x2100)
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#ifdef CONFIG_PDM360NG_BIG
+#define CONFIG_SYS_DDR_SIZE 512 /* MB */
+#elif defined CONFIG_PDM360NG_SMALL
+#define CONFIG_SYS_DDR_SIZE 128 /* MB */
+#else
+#error No memory configuration level defined!
+#endif
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+
+#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000012 /* DDR pin mux and slew rate */
+
+/* DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
+ *
+ * SYS_CFG:
+ * [31:31] MDDRC Soft Reset: Diabled
+ * [30:30] DRAM CKE pin: Enabled
+ * [29:29] DRAM CLK: Enabled
+ * [28:28] Command Mode: Enabled (For initialization only)
+ * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
+ * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
+ * [20:19] Read Test: DON'T USE
+ * [18:18] Self Refresh: Enabled
+ * [17:17] 16bit Mode: Disabled
+ * [16:13] Read Delay: 3
+ * [12:12] Half DQS Delay: Disabled
+ * [11:11] Quarter DQS Delay: Disabled
+ * [10:08] Write Delay: 2
+ * [07:07] Early ODT: Disabled
+ * [06:06] On DIE Termination: Enabled
+ * [05:05] FIFO Overflow Clear: DON'T USE here
+ * [04:04] FIFO Underflow Clear: DON'T USE here
+ * [03:03] FIFO Overflow Pending: DON'T USE here
+ * [02:02] FIFO Underlfow Pending: DON'T USE here
+ * [01:01] FIFO Overlfow Enabled: Enabled
+ * [00:00] FIFO Underflow Enabled: Enabled
+ * TIME_CFG0
+ * [31:16] DRAM Refresh Time: 0 CSB clocks
+ * [15:8] DRAM Command Time: 0 CSB clocks
+ * [07:00] DRAM Precharge Time: 0 CSB clocks
+ * TIME_CFG1
+ * [31:26] DRAM tRFC:
+ * [25:21] DRAM tWR1:
+ * [20:17] DRAM tWRT1:
+ * [16:11] DRAM tDRR:
+ * [10:05] DRAM tRC:
+ * [04:00] DRAM tRAS:
+ * TIME_CFG2
+ * [31:28] DRAM tRCD:
+ * [27:23] DRAM tFAW:
+ * [22:19] DRAM tRTW1:
+ * [18:15] DRAM tCCD:
+ * [14:10] DRAM tRTP:
+ * [09:05] DRAM tRP:
+ * [04:00] DRAM tRPA
+ */
+
+#ifdef CONFIG_PDM360NG_BIG
+#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A40
+#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
+
+#elif defined CONFIG_PDM360NG_SMALL
+#define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A40
+#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG1 0x3CEC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2 0x33310863
+#else
+#error No memory configuration level defined!
+#endif
+
+#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
+
+#define CONFIG_SYS_DDRCMD_NOP 0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
+#define CONFIG_SYS_DDRCMD_EM2 0x01020000 /* EMR2 */
+#define CONFIG_SYS_DDRCMD_EM3 0x01030000 /* EMR3 */
+#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010040 /* EMR with 150 ohm ODT todo: verify*/
+#define CONFIG_SYS_DDRCMD_RES_DLL 0x01000100
+#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
+#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x010107C0 /* EMR with 150 ohm ODT todo: verify*/
+#define CONFIG_SYS_DDRCMD_OCD_EXIT 0x01010440 /* EMR new command with 150 ohm ODT todo: verify*/
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+
+#ifdef CONFIG_PDM360NG_BIG
+#define CONFIG_SYS_FLASH_BASE 0xF0000000 /* start of FLASH-Bank0 */
+#define CONFIG_SYS_FLASH1_BASE 0xF8000000 /* start of FLASH-Bank1 */
+#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size of FLASH-Bank0 in bytes */
+#define CONFIG_SYS_FLASH1_SIZE 0x08000000 /* max flash size of FLASH-Bank1 in bytes */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
+ /* 512 sectors with size 0x40000 for 128MB*/
+#elif defined CONFIG_PDM360NG_SMALL
+#define CONFIG_SYS_FLASH_BASE 0xF0000000 /* start of FLASH-Bank0 */
+#define CONFIG_SYS_FLASH1_BASE 0xF4000000 /* start of FLASH-Bank1 */
+#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size of FLASH-Bank0 in bytes */
+#define CONFIG_SYS_FLASH1_SIZE 0x04000000 /* max flash size of FLASH-Bank1 in bytes */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
+ /* 256 sectors with size 0x40000 for 64MB*/
+#else
+#error No memory configuration level defined!
+#endif
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+#define CONFIG_SYS_SRAM_BASE 0x50000000
+#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
+
+#define CONFIG_SYS_CS0_CFG 0x05059350 /* ALE active low, data size 4bytes */
+#define CONFIG_SYS_CS1_CFG 0x05059350 /* ALE active low, data size 4bytes */
+
+#define CONFIG_SYS_MRAM_BASE 0x50040000
+#define CONFIG_SYS_MRAM_SIZE 0x00020000
+#define CONFIG_SYS_CS2_CFG 0x05059110 /* ALE active low, data size 4bytes */
+
+#define CONFIG_SYS_CS_ALETIMING 0x00000007 /* alt. CS timing for CS0, CS1, CS2 */
+
+/*
+ * NAND FLASH
+ */
+#define CONFIG_CMD_NAND /* enable NAND support */
+#define CONFIG_NAND_MPC5121_NFC
+#define CONFIG_SYS_NAND_BASE 0x40000000
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
+
+/*
+ * Configuration parameters for MPC5121 NAND driver
+ */
+#define CONFIG_FSL_NFC_WIDTH 1
+#define CONFIG_FSL_NFC_WRITE_SIZE 2048
+#define CONFIG_FSL_NFC_SPARE_SIZE 64
+#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
+
+/*
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=f0000000.flash,nor1=f8000000.flash," \
+ "nand0=MPC5121 NAND"
+
+/*
+ * Flash layout
+ */
+#define MTDPARTS_DEFAULT "mtdparts=f0000000.flash:512k(u-boot)," \
+ "256k(environment1)," \
+ "256k(environment2)," \
+ "256k(splash-factory)," \
+ "2m(FIT: recovery)," \
+ "4608k(fs-recovery)," \
+ "256k(splash-customer),"\
+ "5m(FIT: kernel+dtb)," \
+ "64m(rootfs squash)ro," \
+ "51m(userfs ubi);" \
+ "f8000000.flash:-(unused);" \
+ "MPC5121 NAND:1024m(extended-userfs)"
+
+/*
+ * Override partitions in device tree using info
+ * in "mtdparts" environment variable
+ */
+#ifdef CONFIG_CMD_MTDPARTS
+#define CONFIG_FDT_FIXUP_PARTITIONS
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
+#else
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
+#if CONFIG_PSC_CONSOLE != 6
+#error CONFIG_PSC_CONSOLE must be 6
+#endif
+
+#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC6_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC6_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC6_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR
+
+/*
+ * Used PSC UART devices
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_PSC1
+#define CONFIG_SYS_PSC4
+#define CONFIG_SYS_PSC6
+
+/*
+ * Co-processor communication parameters
+ */
+#define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY 5000
+#define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE 38400
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_IIM
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* ST AT24C01 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-Byte Page Write Mode */
+/*
+ * MAC addr in EEPROM
+ */
+#define CONFIG_SYS_I2C_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET 0x10
+/*
+ * Enabled only to delete "ethaddr" before testing
+ * "ethaddr" setting from EEPROM
+ */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC 1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR 0x1F
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_FEC_AN_TIMEOUT 1
+#define CONFIG_HAS_ETH0
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_M41T62 /* use M41T00 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+/* This has to be a multiple of the Flash sector size */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+#undef CONFIG_CMD_FUSE
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
+
+/*
+ * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
+ * to 0xFFFF, watchdog timeouts after about 64s. For details refer
+ * to chapter 36 of the MPC5121e Reference Manual.
+ */
+#undef CONFIG_WATCHDOG /* disable watchdog */
+#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#ifdef CONFIG_CMD_KGDB
+ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE 32768
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
+#define CONFIG_SYS_HID2 HID2_HBE
+
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#ifdef CONFIG_SERIAL_MULTI
+/* POST support */
+#define CONFIG_POST (CONFIG_SYS_POST_COPROC)
+
+#define CONFIG_POST_COPROC {\
+ "Coprocessors communication test", \
+ "coproc_com", \
+ "This test checks communication with coprocessors.", \
+ POST_RAM | POST_ALWAYS | POST_CRITICAL, \
+ &pdm360ng_coprocessor_post_test, \
+ NULL, \
+ NULL, \
+ CONFIG_SYS_POST_COPROC \
+ }
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME pdm360ng
+#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo PDM360NG SAMPLE;" \
+ "echo"
+
+#define CONFIG_BOOTCOMMAND "run env_cont"
+
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+#define OF_CPU "PowerPC,5121 at 0"
+#define OF_SOC_COMPAT "fsl,mpc5121-immr"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc at 80000000/serial at 11600"
+
+/*
+ * Include common options for all mpc5121 boards
+ */
+#include "mpc5121-common.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/post.h b/include/post.h
index 9fcd3ce..d147103 100644
--- a/include/post.h
+++ b/include/post.h
@@ -119,6 +119,7 @@ extern int post_hotkeys_pressed(void);
#define CONFIG_SYS_POST_BSPEC4 0x00080000
#define CONFIG_SYS_POST_BSPEC5 0x00100000
#define CONFIG_SYS_POST_CODEC 0x00200000
+#define CONFIG_SYS_POST_COPROC 0x00400000
#endif /* CONFIG_POST */
diff --git a/post/tests.c b/post/tests.c
index 3224f00..06e9dc0 100644
--- a/post/tests.c
+++ b/post/tests.c
@@ -53,6 +53,7 @@ extern int gdc_post_test (int flags);
extern int fpga_post_test (int flags);
extern int lwmon5_watchdog_post_test(int flags);
extern int sysmon1_post_test(int flags);
+extern int pdm360ng_coprocessor_post_test(int flags);
extern int sysmon_init_f (void);
@@ -286,6 +287,9 @@ struct post_test post_list[] =
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC5
CONFIG_POST_BSPEC5,
#endif
+#if CONFIG_POST & CONFIG_SYS_POST_COPROC
+ CONFIG_POST_COPROC,
+#endif
};
unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test);
--
1.6.3.3
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