[U-Boot] [PATCH 01/28] nios2: add nios2-generic board
Thomas Chou
thomas at wytron.com.tw
Fri Mar 19 08:43:26 CET 2010
This is a generic approach to port u-boot for nios2 boards.
It uses a new set of device drivers, such as the cfi flash, spi
lash, nand flash and new ethernet drivers.
You may find the usage of this approach on the nios2 wiki,
http://nioswiki.com/DasUBoot
In order to better support MMU and NOMMU targets, we will use
virtual addressing in the config file. All references to devices
except for the main memory (sdram), should be mapped to uncached
(bypass), IO region. While the main memory should use cached,
kernel region.
For MMU,
the uncached, IO region is 0xe0000000-0xffffffff.
#define IO_REGION_BASE 0xe0000000
the cached, kernel region is 0xc000000-0xdfffffff.
#define KERNEL_REGION_BASE 0xc0000000
For NOMMU,
the uncached, IO region is 0x8000000-0xffffffff.
#define IO_REGION_BASE 0x80000000
the cached, kernel region is 0x00000000-0x7fffffff.
#define KERNEL_REGION_BASE 0x00000000
In stead of editing the hex number of base address, we will use
the resource header file generated with tools.
An example SMC device def will become,
#define CONFIG_SMC91111_BASE (ENET_BASE | IO_REGION_BASE)
where the ENET_BASE will be defined in the generated file
../board/altera/nios2-generic/custom_fpga.h .
Then when you reassign the base address or turn on/off the MMU,
you will only need to regenerate the header file.
Signed-off-by: Thomas Chou <thomas at wytron.com.tw>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 3 +
board/altera/nios2-generic/Makefile | 57 +++
board/altera/nios2-generic/config.mk | 32 ++
board/altera/nios2-generic/custom_fpga.h | 757 ++++++++++++++++++++++++++++
board/altera/nios2-generic/nios2-generic.c | 67 +++
board/altera/nios2-generic/u-boot.lds | 136 +++++
include/configs/nios2-generic.h | 360 +++++++++++++
9 files changed, 1414 insertions(+), 0 deletions(-)
create mode 100644 board/altera/nios2-generic/Makefile
create mode 100644 board/altera/nios2-generic/config.mk
create mode 100644 board/altera/nios2-generic/custom_fpga.h
create mode 100644 board/altera/nios2-generic/nios2-generic.c
create mode 100644 board/altera/nios2-generic/u-boot.lds
create mode 100644 include/configs/nios2-generic.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 80057ce..2e1976a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -851,6 +851,7 @@ Scott McNutt <smcnutt at psyent.com>
EP1C20 Nios-II
EP1S10 Nios-II
EP1S40 Nios-II
+ nios2-generic Nios-II
#########################################################################
# MicroBlaze Systems: #
diff --git a/MAKEALL b/MAKEALL
index beacb5f..f27694e 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -826,6 +826,7 @@ LIST_nios2=" \
EP1S40 \
PCI5441 \
PK1C20 \
+ nios2-generic \
"
#########################################################################
diff --git a/Makefile b/Makefile
index d801e25..7035169 100644
--- a/Makefile
+++ b/Makefile
@@ -3549,6 +3549,9 @@ PK1C20_config : unconfig
PCI5441_config : unconfig
@$(MKCONFIG) PCI5441 nios2 nios2 pci5441 psyent
+nios2-generic_config : unconfig
+ @$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
+
#========================================================================
## Microblaze
#========================================================================
diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
new file mode 100644
index 0000000..f2be4dd
--- /dev/null
+++ b/board/altera/nios2-generic/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o
+COBJS-$(CONFIG_EPLED) += ../common/epled.o
+COBJS-$(CONFIG_GPIOLED) += ../common/gpioled.o
+COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk
new file mode 100644
index 0000000..dd4577b
--- /dev/null
+++ b/board/altera/nios2-generic/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt at psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for nios2 boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h
new file mode 100644
index 0000000..9b4e0e4
--- /dev/null
+++ b/board/altera/nios2-generic/custom_fpga.h
@@ -0,0 +1,757 @@
+#ifndef _CUSTOM_FPGA_H_
+#define _CUSTOM_FPGA_H_
+
+/*
+ * This file was automatically generated by the swinfo2header utility.
+ *
+ * Created from SOPC Builder system 'NiosII_cycloneII_2c35_full_featured_sopc' in
+ * file './NiosII_cycloneII_2c35_full_featured_sopc.sopcinfo'.
+ */
+
+/*
+ * This file contains macros for module 'cpu' and devices
+ * connected to the following masters:
+ * instruction_master
+ * tightly_coupled_instruction_master_0
+ * data_master
+ * tightly_coupled_data_master_0
+ *
+ * Do not include this header file and another header file created for a
+ * different module or master group at the same time.
+ * Doing so may result in duplicate macro names.
+ * Instead, use the system header file which has macros with unique names.
+ */
+
+/*
+ * Macros for module 'cpu', class 'altera_nios2'.
+ * The macros have no prefix.
+ */
+#define CPU_IMPLEMENTATION "fast"
+#define BIG_ENDIAN 0
+#define CPU_FREQ 85000000
+#define ICACHE_LINE_SIZE 32
+#define ICACHE_LINE_SIZE_LOG2 5
+#define ICACHE_SIZE 4096
+#define DCACHE_LINE_SIZE 32
+#define DCACHE_LINE_SIZE_LOG2 5
+#define DCACHE_SIZE 2048
+#define INITDA_SUPPORTED
+#define FLUSHDA_SUPPORTED
+#define HAS_JMPI_INSTRUCTION
+#define MMU_PRESENT
+#define KERNEL_REGION_BASE 0xc0000000
+#define IO_REGION_BASE 0xe0000000
+#define KERNEL_MMU_REGION_BASE 0x80000000
+#define USER_REGION_BASE 0x0
+#define PROCESS_ID_NUM_BITS 10
+#define TLB_NUM_WAYS 16
+#define TLB_NUM_WAYS_LOG2 4
+#define TLB_PTR_SZ 7
+#define TLB_NUM_ENTRIES 128
+#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc8000000
+#define EXCEPTION_ADDR 0xc6000020
+#define RESET_ADDR 0xc0000000
+#define BREAK_ADDR 0xc2120020
+#define HAS_DEBUG_STUB
+#define HAS_DEBUG_CORE 1
+#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION
+#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION
+#define HAS_EXTRA_EXCEPTION_INFO
+#define CPU_ID_SIZE 1
+#define CPU_ID_VALUE 0x0
+#define HARDWARE_DIVIDE_PRESENT 0
+#define HARDWARE_MULTIPLY_PRESENT 1
+#define HARDWARE_MULX_PRESENT 0
+#define INST_ADDR_WIDTH 28
+#define DATA_ADDR_WIDTH 28
+#define NUM_OF_SHADOW_REG_SETS 0
+
+/*
+ * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash'
+ * The macros are prefixed with 'EXT_FLASH_'.
+ * The prefix is the slave descriptor.
+ */
+#define EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash
+#define EXT_FLASH_COMPONENT_NAME ext_flash
+#define EXT_FLASH_BASE 0x0
+#define EXT_FLASH_SPAN 16777216
+#define EXT_FLASH_END 0xffffff
+#define EXT_FLASH_SETUP_VALUE 45
+#define EXT_FLASH_WAIT_VALUE 160
+#define EXT_FLASH_HOLD_VALUE 35
+#define EXT_FLASH_TIMING_UNITS "ns"
+#define EXT_FLASH_SIZE 16777216
+#define EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8
+#define EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0
+#define EXT_FLASH_MEMORY_INFO_IS_FLASH 1
+#define EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1
+#define EXT_FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+#define EXT_FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR
+
+/*
+ * Macros for device 'cf_ctl', class 'altera_avalon_cf'
+ * The macros are prefixed with 'CF_CTL_'.
+ * The prefix is the slave descriptor.
+ */
+#define CF_CTL_COMPONENT_TYPE altera_avalon_cf
+#define CF_CTL_COMPONENT_NAME cf
+#define CF_CTL_BASE 0x1000000
+#define CF_CTL_SPAN 16
+#define CF_CTL_END 0x100000f
+#define CF_CTL_IRQ 8
+
+/*
+ * Macros for device 'pll', class 'altera_avalon_pll'
+ * The macros are prefixed with 'PLL_'.
+ * The prefix is the slave descriptor.
+ */
+#define PLL_COMPONENT_TYPE altera_avalon_pll
+#define PLL_COMPONENT_NAME pll
+#define PLL_BASE 0x1000020
+#define PLL_SPAN 32
+#define PLL_END 0x100003f
+#define PLL_ARESET "None"
+#define PLL_PFDENA "None"
+#define PLL_LOCKED "None"
+#define PLL_PLLENA "None"
+#define PLL_SCANCLK "None"
+#define PLL_SCANDATA "None"
+#define PLL_SCANREAD "None"
+#define PLL_SCANWRITE "None"
+#define PLL_SCANCLKENA "None"
+#define PLL_SCANACLR "None"
+#define PLL_SCANDATAOUT "None"
+#define PLL_SCANDONE "None"
+#define PLL_CONFIGUPDATE "None"
+#define PLL_PHASECOUNTERSELECT "None"
+#define PLL_PHASEDONE "None"
+#define PLL_PHASEUPDOWN "None"
+#define PLL_PHASESTEP "None"
+
+/*
+ * Macros for device 'pllsysx2', class 'altera_avalon_pll'
+ * The macros are prefixed with 'PLLSYSX2_'.
+ * The prefix is the slave descriptor.
+ */
+#define PLLSYSX2_COMPONENT_TYPE altera_avalon_pll
+#define PLLSYSX2_COMPONENT_NAME pllsysx2
+#define PLLSYSX2_BASE 0x1000040
+#define PLLSYSX2_SPAN 32
+#define PLLSYSX2_END 0x100005f
+#define PLLSYSX2_ARESET "None"
+#define PLLSYSX2_PFDENA "None"
+#define PLLSYSX2_LOCKED "None"
+#define PLLSYSX2_PLLENA "None"
+#define PLLSYSX2_SCANCLK "None"
+#define PLLSYSX2_SCANDATA "None"
+#define PLLSYSX2_SCANREAD "None"
+#define PLLSYSX2_SCANWRITE "None"
+#define PLLSYSX2_SCANCLKENA "None"
+#define PLLSYSX2_SCANACLR "None"
+#define PLLSYSX2_SCANDATAOUT "None"
+#define PLLSYSX2_SCANDONE "None"
+#define PLLSYSX2_CONFIGUPDATE "None"
+#define PLLSYSX2_PHASECOUNTERSELECT "None"
+#define PLLSYSX2_PHASEDONE "None"
+#define PLLSYSX2_PHASEUPDOWN "None"
+#define PLLSYSX2_PHASESTEP "None"
+
+/*
+ * Macros for device 'cf_ide', class 'altera_avalon_cf'
+ * The macros are prefixed with 'CF_IDE_'.
+ * The prefix is the slave descriptor.
+ */
+#define CF_IDE_COMPONENT_TYPE altera_avalon_cf
+#define CF_IDE_COMPONENT_NAME cf
+#define CF_IDE_BASE 0x1000080
+#define CF_IDE_SPAN 64
+#define CF_IDE_END 0x10000bf
+#define CF_IDE_IRQ 9
+
+/*
+ * Macros for device 'ext_ssram', class 'altera_avalon_cy7c1380_ssram'
+ * The macros are prefixed with 'EXT_SSRAM_'.
+ * The prefix is the slave descriptor.
+ */
+#define EXT_SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram
+#define EXT_SSRAM_COMPONENT_NAME ext_ssram
+#define EXT_SSRAM_BASE 0x1400000
+#define EXT_SSRAM_SPAN 2097152
+#define EXT_SSRAM_END 0x15fffff
+#define EXT_SSRAM_SRAM_MEMORY_SIZE 2
+#define EXT_SSRAM_SRAM_MEMORY_UNITS 1048576
+#define EXT_SSRAM_SSRAM_DATA_WIDTH 32
+#define EXT_SSRAM_SSRAM_READ_LATENCY 2
+#define EXT_SSRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define EXT_SSRAM_MEMORY_INFO_HAS_BYTE_LANE 1
+#define EXT_SSRAM_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define EXT_SSRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'enet', class 'altera_avalon_lan91c111'
+ * The macros are prefixed with 'ENET_'.
+ * The prefix is the slave descriptor.
+ */
+#define ENET_COMPONENT_TYPE altera_avalon_lan91c111
+#define ENET_COMPONENT_NAME enet
+#define ENET_BASE 0x2110000
+#define ENET_SPAN 65536
+#define ENET_END 0x211ffff
+#define ENET_IRQ 6
+#define ENET_IS_ETHERNET_MAC 1
+#define ENET_LAN91C111_REGISTERS_OFFSET 768
+#define ENET_LAN91C111_DATA_BUS_WIDTH 32
+
+/*
+ * Macros for device 'timer', class 'altera_avalon_timer'
+ * The macros are prefixed with 'TIMER_'.
+ * The prefix is the slave descriptor.
+ */
+#define TIMER_COMPONENT_TYPE altera_avalon_timer
+#define TIMER_COMPONENT_NAME timer
+#define TIMER_BASE 0x2120800
+#define TIMER_SPAN 32
+#define TIMER_END 0x212081f
+#define TIMER_IRQ 0
+#define TIMER_ALWAYS_RUN 0
+#define TIMER_FIXED_PERIOD 0
+#define TIMER_SNAPSHOT 1
+#define TIMER_PERIOD 10.0
+#define TIMER_PERIOD_UNITS "ms"
+#define TIMER_RESET_OUTPUT 0
+#define TIMER_TIMEOUT_PULSE_OUTPUT 0
+#define TIMER_FREQ 85000000
+#define TIMER_LOAD_VALUE 849999ULL
+#define TIMER_COUNTER_SIZE 32
+#define TIMER_MULT 0.0010
+#define TIMER_TICKS_PER_SEC 100
+
+/*
+ * Macros for device 'high_res_timer', class 'altera_avalon_timer'
+ * The macros are prefixed with 'HIGH_RES_TIMER_'.
+ * The prefix is the slave descriptor.
+ */
+#define HIGH_RES_TIMER_COMPONENT_TYPE altera_avalon_timer
+#define HIGH_RES_TIMER_COMPONENT_NAME high_res_timer
+#define HIGH_RES_TIMER_BASE 0x2120820
+#define HIGH_RES_TIMER_SPAN 32
+#define HIGH_RES_TIMER_END 0x212083f
+#define HIGH_RES_TIMER_IRQ 3
+#define HIGH_RES_TIMER_ALWAYS_RUN 0
+#define HIGH_RES_TIMER_FIXED_PERIOD 0
+#define HIGH_RES_TIMER_SNAPSHOT 1
+#define HIGH_RES_TIMER_PERIOD 10.0
+#define HIGH_RES_TIMER_PERIOD_UNITS "us"
+#define HIGH_RES_TIMER_RESET_OUTPUT 0
+#define HIGH_RES_TIMER_TIMEOUT_PULSE_OUTPUT 0
+#define HIGH_RES_TIMER_FREQ 85000000
+#define HIGH_RES_TIMER_LOAD_VALUE 849ULL
+#define HIGH_RES_TIMER_COUNTER_SIZE 32
+#define HIGH_RES_TIMER_MULT 1.0E-6
+#define HIGH_RES_TIMER_TICKS_PER_SEC 100000
+
+/*
+ * Macros for device 'uart', class 'altera_avalon_uart'
+ * The macros are prefixed with 'UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define UART_COMPONENT_TYPE altera_avalon_uart
+#define UART_COMPONENT_NAME uart
+#define UART_BASE 0x2120840
+#define UART_SPAN 32
+#define UART_END 0x212085f
+#define UART_IRQ 4
+#define UART_BAUD 115200
+#define UART_DATA_BITS 8
+#define UART_FIXED_BAUD 1
+#define UART_PARITY 'N'
+#define UART_STOP_BITS 1
+#define UART_SYNC_REG_DEPTH 2
+#define UART_USE_CTS_RTS 0
+#define UART_USE_EOP_REGISTER 0
+#define UART_SIM_TRUE_BAUD 0
+#define UART_SIM_CHAR_STREAM ""
+#define UART_FREQ 85000000
+
+/*
+ * Macros for device 'button_pio', class 'altera_avalon_pio'
+ * The macros are prefixed with 'BUTTON_PIO_'.
+ * The prefix is the slave descriptor.
+ */
+#define BUTTON_PIO_COMPONENT_TYPE altera_avalon_pio
+#define BUTTON_PIO_COMPONENT_NAME button_pio
+#define BUTTON_PIO_BASE 0x2120860
+#define BUTTON_PIO_SPAN 16
+#define BUTTON_PIO_END 0x212086f
+#define BUTTON_PIO_IRQ 2
+#define BUTTON_PIO_DO_TEST_BENCH_WIRING 1
+#define BUTTON_PIO_DRIVEN_SIM_VALUE 0xf
+#define BUTTON_PIO_HAS_TRI 0
+#define BUTTON_PIO_HAS_OUT 0
+#define BUTTON_PIO_HAS_IN 1
+#define BUTTON_PIO_CAPTURE 1
+#define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define BUTTON_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define BUTTON_PIO_DATA_WIDTH 4
+#define BUTTON_PIO_RESET_VALUE 0x0
+#define BUTTON_PIO_EDGE_TYPE "ANY"
+#define BUTTON_PIO_IRQ_TYPE "EDGE"
+#define BUTTON_PIO_FREQ 85000000
+
+/*
+ * Macros for device 'led_pio', class 'altera_avalon_pio'
+ * The macros are prefixed with 'LED_PIO_'.
+ * The prefix is the slave descriptor.
+ */
+#define LED_PIO_COMPONENT_TYPE altera_avalon_pio
+#define LED_PIO_COMPONENT_NAME led_pio
+#define LED_PIO_BASE 0x2120870
+#define LED_PIO_SPAN 16
+#define LED_PIO_END 0x212087f
+#define LED_PIO_DO_TEST_BENCH_WIRING 0
+#define LED_PIO_DRIVEN_SIM_VALUE 0x0
+#define LED_PIO_HAS_TRI 0
+#define LED_PIO_HAS_OUT 1
+#define LED_PIO_HAS_IN 0
+#define LED_PIO_CAPTURE 0
+#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define LED_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define LED_PIO_DATA_WIDTH 8
+#define LED_PIO_RESET_VALUE 0x0
+#define LED_PIO_EDGE_TYPE "NONE"
+#define LED_PIO_IRQ_TYPE "NONE"
+#define LED_PIO_FREQ 85000000
+
+/*
+ * Macros for device 'lcd_display', class 'altera_avalon_lcd_16207'
+ * The macros are prefixed with 'LCD_DISPLAY_'.
+ * The prefix is the slave descriptor.
+ */
+#define LCD_DISPLAY_COMPONENT_TYPE altera_avalon_lcd_16207
+#define LCD_DISPLAY_COMPONENT_NAME lcd_display
+#define LCD_DISPLAY_BASE 0x2120880
+#define LCD_DISPLAY_SPAN 16
+#define LCD_DISPLAY_END 0x212088f
+
+/*
+ * Macros for device 'seven_seg_pio', class 'altera_avalon_pio'
+ * The macros are prefixed with 'SEVEN_SEG_PIO_'.
+ * The prefix is the slave descriptor.
+ */
+#define SEVEN_SEG_PIO_COMPONENT_TYPE altera_avalon_pio
+#define SEVEN_SEG_PIO_COMPONENT_NAME seven_seg_pio
+#define SEVEN_SEG_PIO_BASE 0x2120890
+#define SEVEN_SEG_PIO_SPAN 16
+#define SEVEN_SEG_PIO_END 0x212089f
+#define SEVEN_SEG_PIO_DO_TEST_BENCH_WIRING 0
+#define SEVEN_SEG_PIO_DRIVEN_SIM_VALUE 0x0
+#define SEVEN_SEG_PIO_HAS_TRI 0
+#define SEVEN_SEG_PIO_HAS_OUT 1
+#define SEVEN_SEG_PIO_HAS_IN 0
+#define SEVEN_SEG_PIO_CAPTURE 0
+#define SEVEN_SEG_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define SEVEN_SEG_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define SEVEN_SEG_PIO_DATA_WIDTH 16
+#define SEVEN_SEG_PIO_RESET_VALUE 0x0
+#define SEVEN_SEG_PIO_EDGE_TYPE "NONE"
+#define SEVEN_SEG_PIO_IRQ_TYPE "NONE"
+#define SEVEN_SEG_PIO_FREQ 85000000
+
+/*
+ * Macros for device 'reconfig_request_pio', class 'altera_avalon_pio'
+ * The macros are prefixed with 'RECONFIG_REQUEST_PIO_'.
+ * The prefix is the slave descriptor.
+ */
+#define RECONFIG_REQUEST_PIO_COMPONENT_TYPE altera_avalon_pio
+#define RECONFIG_REQUEST_PIO_COMPONENT_NAME reconfig_request_pio
+#define RECONFIG_REQUEST_PIO_BASE 0x21208a0
+#define RECONFIG_REQUEST_PIO_SPAN 16
+#define RECONFIG_REQUEST_PIO_END 0x21208af
+#define RECONFIG_REQUEST_PIO_DO_TEST_BENCH_WIRING 0
+#define RECONFIG_REQUEST_PIO_DRIVEN_SIM_VALUE 0x0
+#define RECONFIG_REQUEST_PIO_HAS_TRI 1
+#define RECONFIG_REQUEST_PIO_HAS_OUT 0
+#define RECONFIG_REQUEST_PIO_HAS_IN 0
+#define RECONFIG_REQUEST_PIO_CAPTURE 0
+#define RECONFIG_REQUEST_PIO_BIT_CLEARING_EDGE_REGISTER 0
+#define RECONFIG_REQUEST_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define RECONFIG_REQUEST_PIO_DATA_WIDTH 1
+#define RECONFIG_REQUEST_PIO_RESET_VALUE 0x0
+#define RECONFIG_REQUEST_PIO_EDGE_TYPE "NONE"
+#define RECONFIG_REQUEST_PIO_IRQ_TYPE "NONE"
+#define RECONFIG_REQUEST_PIO_FREQ 85000000
+
+/*
+ * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
+ * The macros are prefixed with 'JTAG_UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart
+#define JTAG_UART_COMPONENT_NAME jtag_uart
+#define JTAG_UART_BASE 0x21208b0
+#define JTAG_UART_SPAN 8
+#define JTAG_UART_END 0x21208b7
+#define JTAG_UART_IRQ 1
+#define JTAG_UART_WRITE_DEPTH 64
+#define JTAG_UART_READ_DEPTH 64
+#define JTAG_UART_WRITE_THRESHOLD 8
+#define JTAG_UART_READ_THRESHOLD 8
+
+/*
+ * Macros for device 'sysid', class 'altera_avalon_sysid'
+ * The macros are prefixed with 'SYSID_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYSID_COMPONENT_TYPE altera_avalon_sysid
+#define SYSID_COMPONENT_NAME sysid
+#define SYSID_BASE 0x21208b8
+#define SYSID_SPAN 8
+#define SYSID_END 0x21208bf
+#define SYSID_ID 1003732523
+#define SYSID_TIMESTAMP 1268227126
+
+/*
+ * Macros for device 'performance_counter', class 'altera_avalon_performance_counter'
+ * The macros are prefixed with 'PERFORMANCE_COUNTER_'.
+ * The prefix is the slave descriptor.
+ */
+#define PERFORMANCE_COUNTER_COMPONENT_TYPE altera_avalon_performance_counter
+#define PERFORMANCE_COUNTER_COMPONENT_NAME performance_counter
+#define PERFORMANCE_COUNTER_BASE 0x2120900
+#define PERFORMANCE_COUNTER_SPAN 64
+#define PERFORMANCE_COUNTER_END 0x212093f
+#define PERFORMANCE_COUNTER_HOW_MANY_SECTIONS 3
+
+/*
+ * Macros for device 'dma', class 'altera_avalon_dma'
+ * The macros are prefixed with 'DMA_'.
+ * The prefix is the slave descriptor.
+ */
+#define DMA_COMPONENT_TYPE altera_avalon_dma
+#define DMA_COMPONENT_NAME dma
+#define DMA_BASE 0x2120a00
+#define DMA_SPAN 32
+#define DMA_END 0x2120a1f
+#define DMA_IRQ 7
+#define DMA_LENGTHWIDTH 13
+#define DMA_ALLOW_BYTE_TRANSACTIONS 1
+#define DMA_ALLOW_HW_TRANSACTIONS 1
+#define DMA_ALLOW_WORD_TRANSACTIONS 1
+#define DMA_ALLOW_DOUBLEWORD_TRANSACTIONS 1
+#define DMA_ALLOW_QUADWORD_TRANSACTIONS 1
+#define DMA_MAX_BURST_SIZE 128
+
+/*
+ * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_EXT_FLASH_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash
+#define DMA_READ_MASTER_EXT_FLASH_COMPONENT_NAME ext_flash
+#define DMA_READ_MASTER_EXT_FLASH_BASE 0x0
+#define DMA_READ_MASTER_EXT_FLASH_SPAN 16777216
+#define DMA_READ_MASTER_EXT_FLASH_END 0xffffff
+#define DMA_READ_MASTER_EXT_FLASH_SETUP_VALUE 45
+#define DMA_READ_MASTER_EXT_FLASH_WAIT_VALUE 160
+#define DMA_READ_MASTER_EXT_FLASH_HOLD_VALUE 35
+#define DMA_READ_MASTER_EXT_FLASH_TIMING_UNITS "ns"
+#define DMA_READ_MASTER_EXT_FLASH_SIZE 16777216
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_IS_FLASH 1
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR
+
+/*
+ * Macros for device 'ext_ssram', class 'altera_avalon_cy7c1380_ssram'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_EXT_SSRAM_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_EXT_SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram
+#define DMA_READ_MASTER_EXT_SSRAM_COMPONENT_NAME ext_ssram
+#define DMA_READ_MASTER_EXT_SSRAM_BASE 0x1400000
+#define DMA_READ_MASTER_EXT_SSRAM_SPAN 2097152
+#define DMA_READ_MASTER_EXT_SSRAM_END 0x15fffff
+#define DMA_READ_MASTER_EXT_SSRAM_SRAM_MEMORY_SIZE 2
+#define DMA_READ_MASTER_EXT_SSRAM_SRAM_MEMORY_UNITS 1048576
+#define DMA_READ_MASTER_EXT_SSRAM_SSRAM_DATA_WIDTH 32
+#define DMA_READ_MASTER_EXT_SSRAM_SSRAM_READ_LATENCY 2
+#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_HAS_BYTE_LANE 1
+#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'lan91c111', class 'altera_avalon_lan91c111'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_LAN91C111_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_LAN91C111_COMPONENT_TYPE altera_avalon_lan91c111
+#define DMA_READ_MASTER_LAN91C111_COMPONENT_NAME lan91c111
+#define DMA_READ_MASTER_LAN91C111_BASE 0x2110000
+#define DMA_READ_MASTER_LAN91C111_SPAN 65536
+#define DMA_READ_MASTER_LAN91C111_END 0x211ffff
+#define DMA_READ_MASTER_LAN91C111_IS_ETHERNET_MAC 1
+#define DMA_READ_MASTER_LAN91C111_LAN91C111_REGISTERS_OFFSET 768
+#define DMA_READ_MASTER_LAN91C111_LAN91C111_DATA_BUS_WIDTH 32
+
+/*
+ * Macros for device 'ddr_sdram_0', class 'ddr_sdram_component_classic'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_DDR_SDRAM_0_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_DDR_SDRAM_0_COMPONENT_TYPE ddr_sdram_component_classic
+#define DMA_READ_MASTER_DDR_SDRAM_0_COMPONENT_NAME ddr_sdram_0
+#define DMA_READ_MASTER_DDR_SDRAM_0_BASE 0x6000000
+#define DMA_READ_MASTER_DDR_SDRAM_0_SPAN 33554432
+#define DMA_READ_MASTER_DDR_SDRAM_0_END 0x7ffffff
+#define DMA_READ_MASTER_DDR_SDRAM_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_READ_MASTER_DDR_SDRAM_0_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_READ_MASTER_DDR_SDRAM_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'tightly_coupled_data_memory', class 'altera_avalon_onchip_memory2'
+ * Path to the device is from the master group 'dma_read_master'.
+ * The macros are prefixed with 'DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_NAME tightly_coupled_data_memory
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_BASE 0x8002000
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SPAN 8192
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_END 0x8003fff
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_data_memory"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_WRITABLE 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_DUAL_PORT 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_VALUE 8192
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_MULTIPLE 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_CONTENTS_INFO ""
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_MEM_CONTENT 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INSTANCE_ID "NONE"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_HEX 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_EXT_FLASH_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash
+#define DMA_WRITE_MASTER_EXT_FLASH_COMPONENT_NAME ext_flash
+#define DMA_WRITE_MASTER_EXT_FLASH_BASE 0x0
+#define DMA_WRITE_MASTER_EXT_FLASH_SPAN 16777216
+#define DMA_WRITE_MASTER_EXT_FLASH_END 0xffffff
+#define DMA_WRITE_MASTER_EXT_FLASH_SETUP_VALUE 45
+#define DMA_WRITE_MASTER_EXT_FLASH_WAIT_VALUE 160
+#define DMA_WRITE_MASTER_EXT_FLASH_HOLD_VALUE 35
+#define DMA_WRITE_MASTER_EXT_FLASH_TIMING_UNITS "ns"
+#define DMA_WRITE_MASTER_EXT_FLASH_SIZE 16777216
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_IS_FLASH 1
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR
+
+/*
+ * Macros for device 'ext_ssram', class 'altera_avalon_cy7c1380_ssram'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_EXT_SSRAM_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_EXT_SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram
+#define DMA_WRITE_MASTER_EXT_SSRAM_COMPONENT_NAME ext_ssram
+#define DMA_WRITE_MASTER_EXT_SSRAM_BASE 0x1400000
+#define DMA_WRITE_MASTER_EXT_SSRAM_SPAN 2097152
+#define DMA_WRITE_MASTER_EXT_SSRAM_END 0x15fffff
+#define DMA_WRITE_MASTER_EXT_SSRAM_SRAM_MEMORY_SIZE 2
+#define DMA_WRITE_MASTER_EXT_SSRAM_SRAM_MEMORY_UNITS 1048576
+#define DMA_WRITE_MASTER_EXT_SSRAM_SSRAM_DATA_WIDTH 32
+#define DMA_WRITE_MASTER_EXT_SSRAM_SSRAM_READ_LATENCY 2
+#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_HAS_BYTE_LANE 1
+#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'lan91c111', class 'altera_avalon_lan91c111'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_LAN91C111_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_LAN91C111_COMPONENT_TYPE altera_avalon_lan91c111
+#define DMA_WRITE_MASTER_LAN91C111_COMPONENT_NAME lan91c111
+#define DMA_WRITE_MASTER_LAN91C111_BASE 0x2110000
+#define DMA_WRITE_MASTER_LAN91C111_SPAN 65536
+#define DMA_WRITE_MASTER_LAN91C111_END 0x211ffff
+#define DMA_WRITE_MASTER_LAN91C111_IS_ETHERNET_MAC 1
+#define DMA_WRITE_MASTER_LAN91C111_LAN91C111_REGISTERS_OFFSET 768
+#define DMA_WRITE_MASTER_LAN91C111_LAN91C111_DATA_BUS_WIDTH 32
+
+/*
+ * Macros for device 'ddr_sdram_0', class 'ddr_sdram_component_classic'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_DDR_SDRAM_0_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_COMPONENT_TYPE ddr_sdram_component_classic
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_COMPONENT_NAME ddr_sdram_0
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_BASE 0x6000000
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_SPAN 33554432
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_END 0x7ffffff
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_WRITE_MASTER_DDR_SDRAM_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'tightly_coupled_data_memory', class 'altera_avalon_onchip_memory2'
+ * Path to the device is from the master group 'dma_write_master'.
+ * The macros are prefixed with 'DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_NAME tightly_coupled_data_memory
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_BASE 0x8002000
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SPAN 8192
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_END 0x8003fff
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_data_memory"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_WRITABLE 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_DUAL_PORT 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_VALUE 8192
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_MULTIPLE 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_CONTENTS_INFO ""
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_MEM_CONTENT 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INSTANCE_ID "NONE"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_HEX 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'epcs_controller', class 'altera_avalon_epcs_flash_controller'
+ * The macros are prefixed with 'EPCS_CONTROLLER_'.
+ * The prefix is the slave descriptor.
+ */
+#define EPCS_CONTROLLER_COMPONENT_TYPE altera_avalon_epcs_flash_controller
+#define EPCS_CONTROLLER_COMPONENT_NAME epcs_controller
+#define EPCS_CONTROLLER_BASE 0x3200000
+#define EPCS_CONTROLLER_SPAN 2048
+#define EPCS_CONTROLLER_END 0x32007ff
+#define EPCS_CONTROLLER_IRQ 5
+#define EPCS_CONTROLLER_REGISTER_OFFSET 512
+#define EPCS_CONTROLLER_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define EPCS_CONTROLLER_MEMORY_INFO_MEM_INIT_FILENAME epcs_controller_boot_rom
+#define EPCS_CONTROLLER_MEMORY_INFO_IS_EPCS 1
+#define EPCS_CONTROLLER_MEMORY_INFO_IS_FLASH 1
+#define EPCS_CONTROLLER_MEMORY_INFO_GENERATE_HEX 1
+#define EPCS_CONTROLLER_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define EPCS_CONTROLLER_MEMORY_INFO_GENERATE_FLASH 1
+#define EPCS_CONTROLLER_MEMORY_INFO_HEX_INSTALL_DIR SIM_DIR
+#define EPCS_CONTROLLER_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+#define EPCS_CONTROLLER_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR
+
+/*
+ * Macros for device 'sdram', class 'ddr_sdram_component_classic'
+ * The macros are prefixed with 'SDRAM_'.
+ * The prefix is the slave descriptor.
+ */
+#define SDRAM_COMPONENT_TYPE ddr_sdram_component_classic
+#define SDRAM_COMPONENT_NAME sdram
+#define SDRAM_BASE 0x6000000
+#define SDRAM_SPAN 33554432
+#define SDRAM_END 0x7ffffff
+#define SDRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define SDRAM_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define SDRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'tightly_coupled_instruction_memory', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'TIGHTLY_COUPLED_INSTRUCTION_MEMORY_'.
+ * The prefix is the slave descriptor.
+ */
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_COMPONENT_NAME tightly_coupled_instruction_memory
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_BASE 0x8000000
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_SPAN 4096
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_END 0x8000fff
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_instruction_memory"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_WRITABLE 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_DUAL_PORT 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_SIZE_VALUE 4096
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_SIZE_MULTIPLE 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_CONTENTS_INFO ""
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_INIT_MEM_CONTENT 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_INSTANCE_ID "NONE"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_GENERATE_HEX 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+/*
+ * Macros for device 'tightly_coupled_data_memory', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'TIGHTLY_COUPLED_DATA_MEMORY_'.
+ * The prefix is the slave descriptor.
+ */
+#define TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2
+#define TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_NAME tightly_coupled_data_memory
+#define TIGHTLY_COUPLED_DATA_MEMORY_BASE 0x8002000
+#define TIGHTLY_COUPLED_DATA_MEMORY_SPAN 8192
+#define TIGHTLY_COUPLED_DATA_MEMORY_END 0x8003fff
+#define TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define TIGHTLY_COUPLED_DATA_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_data_memory"
+#define TIGHTLY_COUPLED_DATA_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define TIGHTLY_COUPLED_DATA_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define TIGHTLY_COUPLED_DATA_MEMORY_WRITABLE 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_DUAL_PORT 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_SIZE_VALUE 8192
+#define TIGHTLY_COUPLED_DATA_MEMORY_SIZE_MULTIPLE 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_CONTENTS_INFO ""
+#define TIGHTLY_COUPLED_DATA_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define TIGHTLY_COUPLED_DATA_MEMORY_INIT_MEM_CONTENT 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define TIGHTLY_COUPLED_DATA_MEMORY_INSTANCE_ID "NONE"
+#define TIGHTLY_COUPLED_DATA_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_HEX 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1
+#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
+
+
+#endif /* _CUSTOM_FPGA_H_ */
diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c
new file mode 100644
index 0000000..d15418d
--- /dev/null
+++ b/board/altera/nios2-generic/nios2-generic.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt at psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas at wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <nios2-io.h>
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("BOARD : %s\n", CONFIG_SYS_BOARD_NAME);
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(bis, CONFIG_SMC91111_BASE);
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+ rc = dm9000_initialize(bis);
+#endif
+
+#ifdef CONFIG_ALTERA_TSE
+ altera_tse_init(bis, CONFIG_SYS_NUM_TSE_MACS);
+#endif
+
+#ifdef CONFIG_ETHOC
+ rc = ethoc_initialize(bis, CONFIG_SYS_ETHOC_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds
new file mode 100644
index 0000000..fa7ed30
--- /dev/null
+++ b/board/altera/nios2-generic/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt at psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = text_base;
+ .text :
+ {
+ cpu/nios2/start.o (.text)
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t*)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ *(.gnu.linkonce.r*)
+ }
+ . = ALIGN (4);
+ _etext = .;
+ PROVIDE (etext = .);
+
+ /* CMD TABLE - sandwich this in between text and data so
+ * the initialization code relocates the command table as
+ * well -- admittedly, this is just pure laziness ;-)
+ */
+ __u_boot_cmd_start = .;
+ .u_boot_cmd :
+ {
+ *(.u_boot_cmd)
+ }
+ . = ALIGN(4);
+ __u_boot_cmd_end = .;
+
+ /* INIT DATA sections - "Small" data (see the gcc -G option)
+ * is always gp-relative. Here we make all init data sections
+ * adjacent to simplify the startup code -- and provide
+ * the global pointer for gp-relative access.
+ */
+ _data = .;
+ .data :
+ {
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+ }
+
+ . = ALIGN(16);
+ _gp = .; /* Global pointer addr */
+ PROVIDE (gp = .);
+
+ .sdata :
+ {
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ }
+ . = ALIGN(4);
+
+ _edata = .;
+ PROVIDE (edata = .);
+
+ /* UNINIT DATA - Small uninitialized data is first so it's
+ * adjacent to sdata and can be referenced via gp. The normal
+ * bss follows. We keep it adjacent to simplify init code.
+ */
+ __bss_start = .;
+ .sbss (NOLOAD) :
+ {
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ }
+ . = ALIGN(4);
+ .bss (NOLOAD) :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.dynbss)
+ *(COMMON)
+ *(.scommon)
+ }
+ . = ALIGN(4);
+ _end = .;
+ PROVIDE (end = .);
+
+ /* DEBUG -- symbol table, string table, etc. etc.
+ */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h
new file mode 100644
index 0000000..024070e
--- /dev/null
+++ b/include/configs/nios2-generic.h
@@ -0,0 +1,360 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt at psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas at wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/altera/nios2-generic/custom_fpga.h"
+#define CONFIG_SYS_BOARD_NAME "custom fpga"
+
+#ifndef KERNEL_REGION_BASE
+# define KERNEL_REGION_BASE 0
+#endif
+
+#ifndef IO_REGION_BASE
+# define IO_REGION_BASE 0x80000000
+#endif
+
+/*
+ * BOARD/CPU
+ */
+#define CONFIG_NIOS2_GENERIC 1 /* custom fpga board */
+#define CONFIG_SYS_CLK_FREQ CPU_FREQ /* core clk */
+
+#define CONFIG_SYS_RESET_ADDR RESET_ADDR /* Hard-reset address */
+#define CONFIG_SYS_EXCEPTION_ADDR EXCEPTION_ADDR /* Exception entry point */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init */
+
+/*
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ */
+#define CONFIG_SYS_ICACHE_SIZE ICACHE_SIZE
+#define CONFIG_SYS_ICACHELINE_SIZE ICACHE_LINE_SIZE
+#define CONFIG_SYS_DCACHE_SIZE DCACHE_SIZE
+#define CONFIG_SYS_DCACHELINE_SIZE DCACHE_LINE_SIZE
+
+/*
+ * MEMORY BASE ADDRESSES
+ */
+#define CONFIG_SYS_SDRAM_BASE (SDRAM_BASE | KERNEL_REGION_BASE) /* SDRAM base addr */
+#define CONFIG_SYS_SDRAM_SIZE (SDRAM_SPAN)
+
+/*
+ * GPIO
+ */
+#define CONFIG_SYS_GPIO_BASE (GPIO_BASE | IO_REGION_BASE)
+#ifdef CONFIG_SYS_GPIO_BASE
+# define CONFIG_SYS_GPIO_SDA 0 /* bitbang i2c sda */
+# define CONFIG_SYS_GPIO_SCL 1 /* bitbang i2c scl */
+# define CONFIG_SYS_GPIO_NRB 2 /* nand flash ready/busy */
+# define CONFIG_SYS_GPIO_HBT 3 /* heartbeat status led */
+#endif
+
+/*
+ * Flash Settings
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+/* #define CONFIG_FLASH_CFI_MTD */
+
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix nios2 flash timing issue */
+#define CONFIG_SYS_FLASH_BASE (EXT_FLASH_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * SPI FLash,EPCS Settings
+ */
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_ALTERA_SPI
+
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_SPI_BASE ((EPCS_CONTROLLER_BASE + EPCS_CONTROLLER_REGISTER_OFFSET) \
+ | IO_REGION_BASE)
+
+/*
+ * NAND Flash
+ */
+/* #define CONFIG_CMD_NAND */
+/* #define CONFIG_NAND_PLAT */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NAND_FLASH_BASE | IO_REGION_BASE)
+#define NIOS2_NAND_PLAT_CLE 2
+#define NIOS2_NAND_PLAT_ALE 3
+#define NAND_PLAT_WRITE_CMD(chip, cmd) \
+ writeb(cmd, (unsigned int)(this->IO_ADDR_W) + (1 << NIOS2_NAND_PLAT_CLE))
+#define NAND_PLAT_WRITE_ADR(chip, cmd) \
+ writeb(cmd, (unsigned int)(this->IO_ADDR_W) + (1 << NIOS2_NAND_PLAT_ALE))
+#define NAND_PLAT_INIT() {}
+#ifdef CONFIG_SYS_GPIO_NRB
+# define NAND_PLAT_DEV_READY(chip) \
+ readl(CONFIG_SYS_GPIO_BASE + ((CONFIG_SYS_GPIO_NRB) << 2))
+#endif
+
+/*
+ * SERIAL
+ */
+#define CONFIG_ALTERA_JTAGUART
+/* #define CONFIG_ALTERA_UART */
+/* #define CONFIG_YANU */
+
+#define CONFIG_SYS_JTAGUART_BASE (JTAG_UART_BASE | IO_REGION_BASE) /* JTAGUART base addr */
+#define CONFIG_SYS_UART_BASE (UART_BASE | IO_REGION_BASE) /* UART base addr */
+#define CONFIG_SYS_UART_FREQ UART_FREQ /* UART clock in freq */
+#define CONFIG_SYS_YANU_BASE (YANU_BASE | IO_REGION_BASE) /* YANU base addr */
+#define CONFIG_SYS_YANU_FREQ YANU_FREQ /* YANU clock in freq */
+
+#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
+#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info */
+
+/*
+ * SYSID
+ */
+#define CONFIG_SYS_NIOS_SYSID_BASE (SYSID_BASE | IO_REGION_BASE) /* Sysid base addr */
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_TIMER_BASE (TIMER_BASE | IO_REGION_BASE) /* Tick timer base addr */
+#define CONFIG_SYS_TIMER_IRQ TIMER_IRQ /* Timer IRQ num */
+#define CONFIG_SYS_TIMER_FREQ TIMER_FREQ /* Timer input freq */
+#define CONFIG_SYS_HZ 1000 /* should be 1000 for flash timing */
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED /* Enable status driver */
+#define CONFIG_EPLED /* Enable LED PIO driver */
+#define CONFIG_SYS_LED_PIO_BASE (LED_PIO_BASE | IO_REGION_BASE) /* LED PIO base addr */
+/* #define CONFIG_GPIOLED */ /* Enable gpio LED driver */
+
+#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
+#define STATUS_LED_STATE 1 /* Blinking */
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* Every 500 msec */
+
+/*
+ * IDE support
+ */
+#define CONFIG_CMD_IDE
+
+#define CONFIG_SYS_PIO_MODE 1
+#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+#define CONFIG_SYS_ATA_BASE_ADDR (CF_IDE_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ATA_STRIDE 4 /* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0 /* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0 /* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x20 /* alternate register offset */
+#define CONFIG_SYS_CF_CTL_BASE (CF_CTL_BASE | IO_REGION_BASE)
+#define CONFIG_IDE_RESET
+
+/*
+ * ETHERNET
+ */
+#define CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+
+#define CONFIG_SMC91111
+#define CONFIG_SMC91111_BASE ((ENET_BASE + ENET_LAN91C111_REGISTERS_OFFSET) \
+ | IO_REGION_BASE) /* Base addr */
+#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
+#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
+
+/* #define CONFIG_DRIVER_DM9000 */
+#define CONFIG_DM9000_BASE (DM9000_BASE | IO_REGION_BASE)
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT 1
+#define CONFIG_DM9000_NO_SROM 1
+/* #define CONFIG_NET_RETRY_COUNT 20 */
+/* #define CONFIG_RESET_PHY_R 1 */
+
+/* #define CONFIG_ALTERA_TSE */
+/* #define CONFIG_MII 1 */
+/* #define CONFIG_CMD_MII */
+#define CONFIG_ETHPRIME "tse0"
+#undef CONFIG_PCI
+
+#define CONFIG_SYS_NUM_TSE_MACS 1
+#define CONFIG_SYS_ALTERA_TSE_0_NAME "tse0"
+#define CONFIG_SYS_ALTERA_TSE_0_BASE (TSE_MAC_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_BASE (SGDMA_RX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_BASE (SGDMA_TX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_IRQ SGDMA_RX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_IRQ SGDMA_TX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM 0
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE (DESCRIPTOR_MEMORY_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN DESCRIPTOR_MEMORY_SPAN
+#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH TSE_MAC_RECEIVE_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH TSE_MAC_TRANSMIT_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_PHY_ADDR 18
+
+/* TSE Supported modes */
+/* GMII/MII = 0 */
+/* RGMII = 1 */
+/* RGMII_ID = 2 */
+/* RGMII_TXID = 3 */
+/* RGMII_RXID = 4 */
+/* SGMII = 5 */
+#define CONFIG_SYS_ALTERA_TSE_0_FLAGS 0x0
+
+
+#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.2.21
+#define CONFIG_SERVERIP 192.168.2.16
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#else
+# undef CONFIG_CMD_BOOTD
+# undef CONFIG_CMD_NET
+# undef CONFIG_CMD_NFS
+# endif
+
+/* #define CONFIG_CMD_SAVES */
+/* #define CONFIG_CMD_JFFS2 */
+/* #define CONFIG_JFFS2_CMDLINE */
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+/* #define CONFIG_CMD_UBI */
+/* #define CONFIG_CMD_UBIFS */
+/* #define CONFIG_RBTREE */
+/* #define CONFIG_MTD_DEVICE */
+/* #define CONFIG_MTD_PARTITIONS */
+/* #define CONFIG_CMD_MTDPARTS */
+/* #define CONFIG_LZO */
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
+#define CONFIG_ENV_SIZE (128 * 1024) /* 128 KByte (1 sector) */
+#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+#if !defined(CONFIG_ENV_IS_IN_FLASH)
+# define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+#endif
+
+/*
+ * MEMORY ORGANIZATION
+ * -Text (code) at top of sdram.
+ * -The heap is placed below the text
+ * -Global data is placed below the heap.
+ * -The stack is placed below global data (&grows down).
+ * -Monitor is the code in flash, we will relocate it to text in sdram
+ */
+#ifdef CONFIG_CMD_UBI
+# define CONFIG_SYS_TEXT_LEN (256 * 1024) /* Reserve 256k */
+#else
+# define CONFIG_SYS_TEXT_LEN (512 * 1024) /* Reserve 512k, ubi is big */
+#endif
+#define CONFIG_SYS_TEXT_BASE (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_TEXT_LEN)
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_RESET_ADDR | IO_REGION_BASE)
+#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_TEXT_LEN
+#define CONFIG_SYS_GBL_DATA_SIZE 256 /* Global data size rsvd */
+#ifdef CONFIG_CMD_UBI /* ubi needs >512KB malloc */
+# define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+#else
+# define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+#endif
+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP /* Provide extended help */
+#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS 16 /* Max command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
+#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
+
+#if defined(CONFIG_NAND_PLAT)
+# define MTD_ENV_SETTINGS \
+ "mtdids=nand0=nand0\0" \
+ "mtdparts=mtdparts=nand0:-(data)\0"
+#elif defined(CONFIG_FLASH_CFI_DRIVER)
+# define MTD_ENV_SETTINGS \
+ "mtdids=nor0=nor0\0" \
+ "mtdparts=mtdparts=nor0:2m(boot),6m(romfs),4m(user),4m(factory)\0"
+#else
+# define MTD_ENV_SETTINGS
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ MTD_ENV_SETTINGS
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#endif /* __CONFIG_H */
--
1.6.6.1
More information about the U-Boot
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