[U-Boot] [PATCH] OpenRD: Reset PCIe endpoint while boot-up through PERST#

[Tanmay Upadhyay]

As per PCIe specifications PERST# line (A11 on the PCIe connector)
should be asserted for minimum 100us. PCIe endpoint comes out of
reset when this line is high.

In case of OpenRD, this line was in tri-state. This might prevent
PCIe devices to appear on the PCIe bus. This patch holds PERST#
line low for 100 us and then sets high while booting.

XGI Vollari Z11 GPU and Intel WiFi 4965 works fine without this fix.
Where as Broadcom's BCM970012 doesn't appear on the PCIe bus without
the fix. There might be few other devices as well which require this.

Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay at einfochips.com>
Signed-off-by: Dhaval Vasa <dhaval.vasa at einfochips.com>
---
 board/Marvell/openrd_base/openrd_base.c |    4 ++++
 board/Marvell/openrd_base/openrd_base.h |    8 ++++----
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c
index c00a08a..b76047a 100644
--- a/board/Marvell/openrd_base/openrd_base.c
+++ b/board/Marvell/openrd_base/openrd_base.c
@@ -103,6 +103,10 @@ int board_init(void)
 
 	kirkwood_mpp_conf(kwmpp_config);
 
+	/* PERST# should be asserted for at least 100 us */
+	udelay(100);
+	writel(readl(KW_GPIO0_BASE) | (1<<7), KW_GPIO0_BASE);
+
 	/*
 	 * arch number of board
 	 */
diff --git a/board/Marvell/openrd_base/openrd_base.h b/board/Marvell/openrd_base/openrd_base.h
index f3daf17..1655c12 100644
--- a/board/Marvell/openrd_base/openrd_base.h
+++ b/board/Marvell/openrd_base/openrd_base.h
@@ -30,10 +30,10 @@
 #ifndef __OPENRD_BASE_H
 #define __OPENRD_BASE_H
 
-#define OPENRD_OE_LOW		(~(1<<28))        /* RS232 / RS485 */
-#define OPENRD_OE_HIGH		(~(1<<2))         /* SD / UART1 */
-#define OPENRD_OE_VAL_LOW		(0)       /* Sel RS232 */
-#define OPENRD_OE_VAL_HIGH		(1 << 2)  /* Sel SD */
+#define OPENRD_OE_LOW		(~((1<<28) | (1<<7)))  /* RS232 / RS485, PCIe */
+#define OPENRD_OE_HIGH		(~(1<<2))              /* SD / UART1 */
+#define OPENRD_OE_VAL_LOW	0             /* Sel RS232, PCIe reset */
+#define OPENRD_OE_VAL_HIGH	(1 << 2)      /* Sel SD */
 
 /* PHY related */
 #define MV88E1116_LED_FCTRL_REG		10
-- 
1.6.6.1