[U-Boot] [PATCH V3][NEXT] Davinci: add support for the ea20 board

[Ben Gardiner]

On Mon, Nov 15, 2010 at 4:46 AM, Stefano Babic <sbabic at denx.de> wrote:
>
> This board uses the OMAP-L138 SOM stacked on a
> custom baseboard. It supports SPI Flash, Ethernet
> with RMII.
>
> Signed-off-by: Stefano Babic <sbabic at denx.de>
> ---
> Changes since V2:
>  - Rebased on the following patch(Sughosh Ganu):
> [...]
> diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
> new file mode 100644
> index 0000000..e3e07a3
> --- /dev/null
> +++ b/board/davinci/ea20/ea20.c
> @@ -0,0 +1,237 @@
> +/*
> + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * Based on da830evm.c. Original Copyrights follow:

It seems to me that this file is based off of da850evm.c; the
da850ev.c file contains this comment which is where it likely came
from. If it is based on da850evm.c then I think the file's comment
should reflect this.

> [...]
> +
> +static void da850_emac_mii_mode_sel(int mode_sel)
> +{
> +       int val;
> +
> +       val = readl(&davinci_syscfg_regs->cfgchip3);
> +       if (mode_sel == 0)
> +               val &= ~(1 << 8);
> +       else
> +               val |= (1 << 8);
> +       writel(val, &davinci_syscfg_regs->cfgchip3);
> +}

This is a function common to any da850 board using RMII, could it be
extracted to a shared .c file?

> [...]
> +#ifdef CONFIG_NAND_DAVINCI
> +       /*
> +        * NAND CS setup - cycle counts based on da850evm NAND timings in the
> +        * Linux kernel @ 25MHz EMIFA
> +        */
> +       writel((DAVINCI_ABCR_WSETUP(0) |
> +               DAVINCI_ABCR_WSTROBE(0) |
> +               DAVINCI_ABCR_WHOLD(0) |
> +               DAVINCI_ABCR_RSETUP(0) |
> +               DAVINCI_ABCR_RSTROBE(1) |
> +               DAVINCI_ABCR_RHOLD(0) |
> +               DAVINCI_ABCR_TA(0) |
> +               DAVINCI_ABCR_ASIZE_8BIT),
> +              &davinci_emif_regs->ab2cr); /* CS3 */
> +#endif

This looks like it was copied from da850evm.c; note that these timings
are based on the integer multiples of EMA_CLK periods that meet the
timing specifications of the NAND chip found on the UI board. A
different part could have different timings...

Also, from your description of the ea20: "It supports SPI Flash,
Ethernet with RMII." -- there is no NAND support.

> [...]
> +int board_eth_init(bd_t *bis)
> +{
> +       if (!davinci_emac_initialize()) {
> +               printf("Error: Ethernet init failed!\n");
> +               return -1;
> +       }
> +
> +       /*
> +        * This board has a RMII PHY. However, the MDC line on the SOM
> +        * must not be disabled (there is no MII PHY on the
> +        * baseboard) via the GPIO2[6], because this pin
> +        * disables at the same time the SPI flash.
> +        */
> +
> +       return 0;
> +}
> +#endif /* CONFIG_DRIVER_TI_EMAC */

Perhaps it would be prudent to _enable_ the MDC line via the GPIO2[6]
pin instead of a no-op.


--
Best Regards,
Ben Gardiner

---
Nanometrics Inc.
http://www.nanometrics.ca