[U-Boot] [PATCH] mpc83xx: Make it boot again

[Scott Wood]

On Wed, 17 Nov 2010 17:57:53 +0100
Joakim Tjernlund <joakim.tjernlund at transmode.se> wrote:

> > From: Liu Dave-R63238 <r63238 at freescale.com>
> > To: Andre Schwarz <andre.schwarz at matrix-vision.de>
> > Cc: Wood Scott-B07421 <B07421 at freescale.com>, Kumar at theia.denx.de, Tabi Timur-B04825 <B04825 at freescale.com>, Phillips Kim-R1AAHA <R1AAHA at freescale.com>, Gala <galak at kernel.crashing.org>, U-Boot List <u-boot at lists.denx.de>
> > Date: 2010/11/15 17:58
> > Subject: Re: [U-Boot] [PATCH] mpc83xx: Make it boot again
> > Sent by: u-boot-bounces at lists.denx.de
> >
> > > The experts found an issue within init code and it looks like a proper
> > > patch will be added to mainline shortly.
> > > The discussion of the proper fix is right in this thread ...
> >
> > It should be timing issue in the SoC, software did not have a proper
> > process to handle
> > IMMR registers accessing.
> >
> > I agree Kumar on this.
> > Adding the read back with load is needing for the LAW window changing.
> > And something like sync/eieio instruction also need to be added between
> > stw and lwz...
> > to have a proper order accessing.
> 
> After adding some more stuff in start.S I find that a lwz isn't
> enough. An extra isync fixes this though
> 
>  lwz r4, LBLAWAR1(r3)
>  isync
> 
> So something is missing but what? I guess isync isn't it either but
> it works for now.

As I said before, the sequence we follow in the normal I/O accessors is:

lwz	r4, LBLAWAR1(r3)
twi	0, r4, 0
isync

Unless we have a good reason to deviate from that -- or a good reason
why that sequence is not necessary in general -- I think we should
use it here as well.

-Scott