[U-Boot] [PATCH] mpc83xx: Make it boot again

[Joakim Tjernlund]

Scott Wood <scottwood at freescale.com> wrote on 2010/11/17 20:03:25:
>
> On Wed, 17 Nov 2010 18:26:02 +0100
> Joakim Tjernlund <joakim.tjernlund at transmode.se> wrote:
>
> > Scott Wood <scottwood at freescale.com> wrote on 2010/11/17 18:05:37:
> > >
> > > On Wed, 17 Nov 2010 17:57:53 +0100
> > > Joakim Tjernlund <joakim.tjernlund at transmode.se> wrote:
> > >
> > > > After adding some more stuff in start.S I find that a lwz isn't
> > > > enough. An extra isync fixes this though
> > > >
> > > >  lwz r4, LBLAWAR1(r3)
> > > >  isync
> > > >
> > > > So something is missing but what? I guess isync isn't it either but
> > > > it works for now.
> > >
> > > As I said before, the sequence we follow in the normal I/O accessors is:
> > >
> > > lwz   r4, LBLAWAR1(r3)
> > > twi   0, r4, 0
> > > isync
> >
> > That works too. I do wonder if twi ..,r4,.. is correct though?
> > Even a
> >  lwz r4, LBLAWAR1(r3)
> >  nop
> > works.
>
> Just because you can get away with something doesn't mean that it's
> theoretically sufficient.  We got away with nothing at all until
> recently.

Right, was just saying ..

>
> The "load, conditional branch, isync" sequence is documented in the
> architecture manual (1.7.1), "even if the effects of the 'dependency'
> are independent of the value loaded".

So it doesn't matter what address you do twi on?
Still, it would make a little more sense if
it read twi 0,r3,0

   Jocke