[U-Boot] [PATCH v5 1/1] imx: Get fec mac address from fuse

[Jason Liu]

Hi, Stefano,

2010/11/18 Stefano Babic <sbabic at denx.de>:
> On 11/18/2010 09:09 AM, Jason Liu wrote:
>> The patch is to support getting FEC MAC address from fuse bank.
>>
>> Signed-off-by: Jason Liu <r64343 at freescale.com>
>
> Hi Jason,
>
>> +     for (i = 0; i < 6; i++)
>> +             mac[i] = readl(&fuse->mac_addr[i]);
>
> This works, but implicitely converts the integer to a char. Should we
> add a mask to make clear that only the LSB of the read value is taken ?

In fact, I think it's not need to add a mask to do it. But for
clearance, I can add it per your request.

 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;

>
>> +     for (i = 0; i < 6; i++)
>> +             mac[6-1-i] = readl(&fuse->mac_addr[i]);
>                     ^
>                     |--- missing spaces

do you mean it need change to mac[6 - 1 - i] ?

>
>> +
>> +struct iim_regs {
>> +     u32     stat;
>> +     u32     statm;
>> +     u32     err;
>> +     u32     emask;
>> +     u32     fctl;
>> +     u32     ua;
>> +     u32     la;
>> +     u32     sdat;
>> +     u32     prev;
>> +     u32     srev;
>> +     u32     preg_p;
>> +     u32     scs0;
>> +     u32     scs1;
>> +     u32     scs2;
>> +     u32     scs3;
>> +     u32     res0[0x1f1];
>> +     struct fuse_bank {
>> +             u32     fuse_regs[0x20];
>> +             u32     fuse_rsvd[0xe0];
>> +     } bank[4];
>
> I see a discrepancy between i.mx27 and i.mx51 and it is not clear to me
> if it is correct. Both processor has the same register map (at least as
> meaning) until scs3. The offset for this register is for both processors
> 0x3c. The fuse bank0 starts for both processor at the offset 0x804, as I
> see in manuals. However, you reserved in one case 0x1f0 integers and in
> the other case 0x1f1. Is it correct ?

I think that the original mx27 code should be wrong. I will fix it.
Thank you for your review.

>
> Best regards,
> Stefano Babic
>
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