[U-Boot] migration from Micron to ISSI RAM

[Mauro Marinho]

Hi there,
     It's my first contact to the group. I just started working with U-boot
from my Job here in Brazil. Does anyone has already worked with any of the
RAM's below? both 2 Meg x 16 x 4 banks:

   - Micron - MT48LC8M16A2;
   - ISSI - IS42S16800E -75ETL;

 I got the mission to make the  necessary software  changes to make a
MPC5200B board to work with our new RAM from ISSI provider, model
IS42S16800E which is a 128Mb (16MB), 133Mhz, CAS = 2. So it means the board
was already working fine with the OLD micron RAM. Offcourse I tried to load
the same u-boot version to experiment. It failed with the same error
below(bolded). I have the "*MPC5200B SDRAM Initialization and Configuration"
* document I used as reference.

     There are 2 CI's on CS0 and CS1 is disabled. So we have 32MB(2x16MB)
available onBoard. I noticed from the study on each datasheet that Micron
was configured with CAS Latency = 3 the only clear difference from
ISSI(CAS=2), and some small timing differences I used on calculations. Then
i've changed the *control, mode, config1 and config2* REGISTERS to
corroborate ISSI's datasheet.
     After that, I compiled and loaded U-boot on the Board. Then, I got a
WRITE error on screen BELOW :

*U-Boot 1.1.6.Autotrac-R2a-g6b4fc061-dirty (Nov 23 2010 - 10:53:30)*
*
*
*CPU:   MPC5200 v1.2, Core v1.1 at 396 MHz*
*       Bus 132 MHz, IPB 66 MHz, PCI 33 MHz*
*Board: Autotrac UCC*
*DRAM:  32 MB*
*Memory (date line) error at 00000000, wrote aaaaaaaaaaaaaaaa, read
89abcdef89abcdef !*
*Memory (date line) error at 00000000, wrote cccccccccccccccc, read
89abcdef89abcdef !*
*...*

What could it be? where should I pay more attention? doesn't it look like a
timing problem?



The header portion extracted;
/*
 * SDRAM configuration
 */
/* 2x IS42S16800E - 7.5 ns SDRAMS = 32 MegaBytes Total */
*#define CFG_DRAM_DDR           0*           /* 0 = SDR mode;   1 = DDR
mode*/
#*define CFG_DRAM_EMODE   0 *          /* DDR usage*/
*#define CFG_DRAM_MODE   0x008D*          //* pg.250 0.1100.11[01] (CAS=2
burst=8) */
*#define CFG_DRAM_CONTROL   0x504F0000*   /* pg.251 refresh=0xF half the
max(64ms) */
*#define CFG_DRAM_CONFIG1   0xC2222A00*  // 15/7.5    oldValue=0xD2333A00 /*
pg.254 */
*#define CFG_DRAM_CONFIG2   0x8AC70000*  //* 0x8AD70000 pg.255 */
*#define CFG_DRAM_TAP_DEL   0x01*     /* pg.146  */
*#define CFG_DRAM_RAM_SIZE 0x18  *           /* Bitset 11000 -> 32M pg.126
*/


If there's any missing info, please let me know.
My Best Regards,
--
Mauro César