[U-Boot] [PATCH 27/37] Blackfin: bct-brettl2: new board port
Mike Frysinger
vapier at gentoo.org
Sat Oct 2 22:05:48 CEST 2010
From: Peter Meerwald <pmeerw at pmeerw.net>
Signed-off-by: Peter Meerwald <pmeerw at pmeerw.net>
Signed-off-by: Mike Frysinger <vapier at gentoo.org>
---
MAINTAINERS | 4 +
board/bct-brettl2/Makefile | 51 +++++++++++
board/bct-brettl2/bct-brettl2.c | 123 +++++++++++++++++++++++++
board/bct-brettl2/cled.c | 32 +++++++
board/bct-brettl2/config.mk | 35 +++++++
board/bct-brettl2/gpio_cfi_flash.c | 4 +
board/bct-brettl2/smsc9303.c | 176 ++++++++++++++++++++++++++++++++++++
board/bct-brettl2/smsc9303.h | 9 ++
boards.cfg | 1 +
include/configs/bct-brettl2.h | 155 +++++++++++++++++++++++++++++++
10 files changed, 590 insertions(+), 0 deletions(-)
create mode 100644 board/bct-brettl2/Makefile
create mode 100644 board/bct-brettl2/bct-brettl2.c
create mode 100644 board/bct-brettl2/cled.c
create mode 100644 board/bct-brettl2/config.mk
create mode 100644 board/bct-brettl2/gpio_cfi_flash.c
create mode 100644 board/bct-brettl2/smsc9303.c
create mode 100644 board/bct-brettl2/smsc9303.h
create mode 100644 include/configs/bct-brettl2.h
diff --git a/MAINTAINERS b/MAINTAINERS
index b0cc825..d6a701d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1041,6 +1041,10 @@ Brent Kandetzki <brentk at teleco.com>
IP04 BF532
+Peter Meerwald <devel at bct-electronic.com>
+
+ bct-brettl2 BF536
+
#########################################################################
# End of MAINTAINERS list #
#########################################################################
diff --git a/board/bct-brettl2/Makefile b/board/bct-brettl2/Makefile
new file mode 100644
index 0000000..cf99d29
--- /dev/null
+++ b/board/bct-brettl2/Makefile
@@ -0,0 +1,51 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o gpio_cfi_flash.o cled.o
+COBJS-$(CONFIG_BFIN_MAC) += smsc9303.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/bct-brettl2/bct-brettl2.c b/board/bct-brettl2/bct-brettl2.c
new file mode 100644
index 0000000..de5b9ff
--- /dev/null
+++ b/board/bct-brettl2/bct-brettl2.c
@@ -0,0 +1,123 @@
+/*
+ * U-boot - main board file for BCT brettl2
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+#include <asm/gpio.h>
+#include <asm/net.h>
+#include <net.h>
+#include <netdev.h>
+#include <miiphy.h>
+
+#include "../cm-bf537e/gpio_cfi_flash.h"
+#include "smsc9303.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: bct-brettl2 board\n");
+ printf(" Support: http://www.bct-electronic.com/\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int retry = 3;
+ int ret;
+
+ ret = bfin_EMAC_initialize(bis);
+
+ uchar enetaddr[6];
+ if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ printf("setting MAC %pM\n", enetaddr);
+ }
+ puts(" ");
+
+ puts("initialize SMSC LAN9303i ethernet switch\n");
+
+ while (retry-- > 0) {
+ if (init_smsc9303i_mii())
+ return ret;
+ }
+
+ return ret;
+}
+#endif
+
+static void init_tlv320aic31(void)
+{
+ puts("Audio: setup TIMER0 to enable 16.384 MHz clock for tlv320aic31\n");
+ peripheral_request(P_TMR0, "tlv320aic31 clock");
+ bfin_write_TIMER0_CONFIG(0x020d);
+ bfin_write_TIMER0_PERIOD(0x0008);
+ bfin_write_TIMER0_WIDTH(0x0008/2);
+ bfin_write_TIMER_ENABLE(bfin_read_TIMER_ENABLE() | 1);
+ SSYNC();
+ udelay(10000);
+
+ puts(" resetting tlv320aic31\n");
+
+ gpio_request(GPIO_PF2, "tlv320aic31");
+ gpio_direction_output(GPIO_PF2, 0);
+ udelay(10000);
+ gpio_direction_output(GPIO_PF2, 1);
+ udelay(10000);
+ gpio_free(GPIO_PF2);
+}
+
+static void init_mute_pin(void)
+{
+ printf(" unmute class D amplifier\n");
+
+ gpio_request(GPIO_PF5, "mute");
+ gpio_direction_output(GPIO_PF5, 1);
+ gpio_free(GPIO_PF5);
+}
+
+/* sometimes LEDs (speech, status) are still on after reboot, turn 'em off */
+static void turn_leds_off(void)
+{
+ printf(" turn LEDs off\n");
+
+ gpio_request(GPIO_PF6, "led");
+ gpio_direction_output(GPIO_PF6, 0);
+ gpio_free(GPIO_PF6);
+
+ gpio_request(GPIO_PF15, "led");
+ gpio_direction_output(GPIO_PF15, 0);
+ gpio_free(GPIO_PF15);
+}
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+ gpio_cfi_flash_init();
+ init_tlv320aic31();
+ init_mute_pin();
+ turn_leds_off();
+
+ return 0;
+}
diff --git a/board/bct-brettl2/cled.c b/board/bct-brettl2/cled.c
new file mode 100644
index 0000000..9e73c57
--- /dev/null
+++ b/board/bct-brettl2/cled.c
@@ -0,0 +1,32 @@
+/*
+ * cled.c - control color led
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+
+int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr = 0x20000000 + 0x200000; // AMS2
+ uchar data;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ data = simple_strtoul(argv[1], NULL, 10);
+ outb(data, addr);
+
+ printf("cled, write %02x\n", data);
+
+ return 0;
+}
+
+U_BOOT_CMD(cled, 2, 0, do_cled,
+ "set/clear color LED",
+ "");
diff --git a/board/bct-brettl2/config.mk b/board/bct-brettl2/config.mk
new file mode 100644
index 0000000..dfd9456
--- /dev/null
+++ b/board/bct-brettl2/config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+CONFIG_BFIN_CPU = bf536-0.3
+
+CFLAGS_lib += -O2
+CFLAGS_lib/lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bct-brettl2/gpio_cfi_flash.c b/board/bct-brettl2/gpio_cfi_flash.c
new file mode 100644
index 0000000..b385c7f
--- /dev/null
+++ b/board/bct-brettl2/gpio_cfi_flash.c
@@ -0,0 +1,4 @@
+#define GPIO_PIN_1 GPIO_PG5
+#define GPIO_PIN_2 GPIO_PG6
+#define GPIO_PIN_3 GPIO_PG7
+#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/bct-brettl2/smsc9303.c b/board/bct-brettl2/smsc9303.c
new file mode 100644
index 0000000..15eea7a
--- /dev/null
+++ b/board/bct-brettl2/smsc9303.c
@@ -0,0 +1,176 @@
+/*
+ * smsc9303.c - routines to initialize SMSC 9303 switch
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <miiphy.h>
+
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+
+static int smc9303i_write_mii(unsigned char addr, unsigned char reg, unsigned short data)
+{
+ const char *devname = miiphy_get_current_dev();
+
+ if (!devname)
+ return 0;
+
+ if (miiphy_write(devname, addr, reg, data) != 0)
+ return 0;
+
+ return 1;
+}
+
+static int smc9303i_write_reg(unsigned short reg, unsigned int data)
+{
+ const char *devname = miiphy_get_current_dev();
+ unsigned char mii_addr = 0x10 | (reg >> 6);
+ unsigned char mii_reg = (reg & 0x3c) >> 1;
+
+ if (!devname)
+ return 0;
+
+ if (miiphy_write(devname, mii_addr, mii_reg|0, data & 0xffff) != 0)
+ return 0;
+
+ if (miiphy_write(devname, mii_addr, mii_reg|1, data >> 16) != 0)
+ return 0;
+
+ return 1;
+}
+
+static int smc9303i_read_reg(unsigned short reg, unsigned int *data)
+{
+ const char *devname = miiphy_get_current_dev();
+ unsigned char mii_addr = 0x10 | (reg >> 6);
+ unsigned char mii_reg = (reg & 0x3c) >> 1;
+ unsigned short tmp1, tmp2;
+
+ if (!devname)
+ return 0;
+
+ if (miiphy_read(devname, mii_addr, mii_reg|0, &tmp1) != 0)
+ return 0;
+
+ if (miiphy_read(devname, mii_addr, mii_reg|1, &tmp2) != 0)
+ return 0;
+
+ *data = (tmp2 << 16) | tmp1;
+
+ return 1;
+}
+
+#if 0
+static int smc9303i_read_mii(unsigned char addr, unsigned char reg, unsigned short *data)
+{
+ const char *devname = miiphy_get_current_dev();
+
+ if (!devname)
+ return 0;
+
+ if (miiphy_read(devname, addr, reg, data) != 0)
+ return 0;
+
+ return 1;
+}
+#endif
+
+typedef struct {
+ unsigned short reg;
+ unsigned int value;
+} smsc9303i_config_entry1_t;
+
+static const smsc9303i_config_entry1_t smsc9303i_config_table1[] =
+{
+ {0x1a0, 0x00000006}, /* Port 1 Manual Flow Control Register */
+ {0x1a4, 0x00000006}, /* Port 2 Manual Flow Control Register */
+ {0x1a8, 0x00000006}, /* Port 0 Manual Flow Control Register */
+};
+
+typedef struct
+{
+ unsigned char addr;
+ unsigned char reg;
+ unsigned short value;
+} smsc9303i_config_entry2_t;
+
+static const smsc9303i_config_entry2_t smsc9303i_config_table2[] =
+{
+ {0x01, 0x00, 0x0100}, /* Port0 PHY Basic Control Register */
+ {0x02, 0x00, 0x1100}, /* Port1 PHY Basic Control Register */
+ {0x03, 0x00, 0x1100}, /* Port2 PHY Basic Control Register */
+
+ {0x01, 0x04, 0x0001}, /* Port0 PHY Auto-Negotiation Advertisement Register */
+ {0x02, 0x04, 0x2de1}, /* Port1 PHY Auto-Negotiation Advertisement Register */
+ {0x03, 0x04, 0x2de1}, /* Port2 PHY Auto-Negotiation Advertisement Register */
+
+ {0x01, 0x11, 0x0000}, /* Port0 PHY Mode Control/Status Register */
+ {0x02, 0x11, 0x0000}, /* Port1 PHY Mode Control/Status Register */
+ {0x03, 0x11, 0x0000}, /* Port2 PHY Mode Control/Status Register */
+
+ {0x01, 0x12, 0x0021}, /* Port0 PHY Special Modes Register */
+ {0x02, 0x12, 0x00e2}, /* Port1 PHY Special Modes Register */
+ {0x03, 0x12, 0x00e3}, /* Port2 PHY Special Modes Register */
+ {0x01, 0x1b, 0x0000}, /* Port0 PHY Special Control/Status Indication Register */
+ {0x02, 0x1b, 0x0000}, /* Port1 PHY Special Control/Status Indication Register */
+ {0x03, 0x1b, 0x0000}, /* Port2 PHY Special Control/Status Indication Register */
+ {0x01, 0x1e, 0x0000}, /* Port0 PHY Interrupt Source Flags Register */
+ {0x02, 0x1e, 0x0000}, /* Port1 PHY Interrupt Source Flags Register */
+ {0x03, 0x1e, 0x0000}, /* Port2 PHY Interrupt Source Flags Register */
+};
+
+int init_smsc9303i_mii(void)
+{
+ unsigned int data;
+ unsigned int i;
+
+ printf(" reset SMSC LAN9303i\n");
+
+ gpio_request(GPIO_PG10, "smsc9303");
+ gpio_direction_output(GPIO_PG10, 0);
+ udelay(10000);
+ gpio_direction_output(GPIO_PG10, 1);
+ udelay(10000);
+
+ gpio_free(GPIO_PG10);
+
+#if defined(CONFIG_MII_INIT)
+ mii_init();
+#endif
+
+ printf(" write SMSC LAN9303i configuration\n");
+
+ if (!smc9303i_read_reg(0x50, &data))
+ return 0;
+
+ if ((data >> 16) != 0x9303) {
+ /* chip id not found */
+ printf(" error identifying SMSC LAN9303i\n");
+ return 0;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table1); i++) {
+ const smsc9303i_config_entry1_t *entry = &smsc9303i_config_table1[i];
+
+ if (!smc9303i_write_reg(entry->reg, entry->value)) {
+ printf(" error writing SMSC LAN9303i configuration\n");
+ return 0;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table2); i++) {
+ const smsc9303i_config_entry2_t *entry = &smsc9303i_config_table2[i];
+
+ if (!smc9303i_write_mii(entry->addr, entry->reg, entry->value)) {
+ printf(" error writing SMSC LAN9303i configuration\n");
+ return 0;
+ }
+ }
+
+ return 1;
+}
diff --git a/board/bct-brettl2/smsc9303.h b/board/bct-brettl2/smsc9303.h
new file mode 100644
index 0000000..a4ba40e
--- /dev/null
+++ b/board/bct-brettl2/smsc9303.h
@@ -0,0 +1,9 @@
+/*
+ * smsc9303.h - routines to initialize SMSC 9303 switch
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+int init_smsc9303i_mii(void);
diff --git a/boards.cfg b/boards.cfg
index 8689ba4..86838f2 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -279,6 +279,7 @@ atstk1004 avr32 at32ap atstk1000 atmel at32ap700x
atstk1006 avr32 at32ap atstk1000 atmel at32ap700x
favr-32-ezkit avr32 at32ap - earthlcd at32ap700x
hammerhead avr32 at32ap - miromico at32ap700x
+bct-brettl2 blackfin blackfin
bf518f-ezbrd blackfin blackfin
bf526-ezbrd blackfin blackfin
bf527-ad7160-eval blackfin blackfin
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
new file mode 100644
index 0000000..09691d3
--- /dev/null
+++ b/include/configs/bct-brettl2.h
@@ -0,0 +1,155 @@
+/*
+ * U-boot - Configuration file for BF536 brettl2 board
+ */
+
+#ifndef __CONFIG_BCT_BRETTL2_H__
+#define __CONFIG_BCT_BRETTL2_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ 16384000
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF 0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
+/* 1 = bypass PLL */
+#define CONFIG_PLL_BYPASS 0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-63 (where 0 means 64) */
+#define CONFIG_VCO_MULT 24
+/* CCLK_DIV controls the core clock divider */
+/* Values can be 1, 2, 4, or 8 ONLY */
+#define CONFIG_CCLK_DIV 1
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 1-15 */
+#define CONFIG_SCLK_DIV 3
+#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH 9
+#define CONFIG_MEM_SIZE 32
+
+
+/*
+ * SDRAM Settings
+ */
+#define CONFIG_EBIU_SDRRC_VAL 0x07f6
+#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK 1
+#define CONFIG_BFIN_MAC 1
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HOSTNAME brettl2
+#define CONFIG_IPADDR 192.168.233.224
+#define CONFIG_GATEWAYIP 192.168.233.1
+#define CONFIG_SERVERIP 192.168.233.53
+#define CONFIG_ROOTPATH /romfs/brettl2
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
+#endif
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 135
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET 0x4000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+ arch/blackfin/cpu/traps.o (.text .text.*); \
+ arch/blackfin/cpu/interrupt.o (.text .text.*); \
+ arch/blackfin/cpu/serial.o (.text .text.*); \
+ common/dlmalloc.o (.text .text.*); \
+ lib/crc32.o (.text .text.*); \
+ . = DEFINED(env_offset) ? env_offset : .; \
+ common/env_embedded.o (.text .text.*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C 1
+#define CONFIG_HARD_I2C 1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_LOADADDR 0x800000
+#define CONFIG_MISC_INIT_R
+#define CONFIG_UART_CONSOLE 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+/* disable unnecessary features */
+#undef CONFIG_BOOTM_RTEMS
+#undef CONFIG_BZIP2
+#undef CONFIG_KALLSYMS
+
+#endif
--
1.7.3.1
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