[U-Boot] [PATCH] logodl: : remove code for yet another corpse
Marek Vasut
marek.vasut at gmail.com
Wed Oct 6 05:32:51 CEST 2010
Dne Út 5. října 2010 22:03:23 Wolfgang Denk napsal(a):
> The logodl board has long been unmaintained and left broken.
> As obviously nobody is interestedin that code any more, we may as well
> remove it.
I'd like to NACK it as it's sad to kill a board, but whatever. I don't own one.
>
> Signed-off-by: Wolfgang Denk <wd at denx.de>
> Cc: August Hoeraendl <august.hoerandl at gmx.at>
> Cc: Robert Schwebel <r.schwebel at pengutronix.de>
> Cc: Marek Vasut <marek.vasut at gmail.com>
> ---
> CREDITS | 6 +-
> board/logodl/Makefile | 51 ---
> board/logodl/config.mk | 15 -
> board/logodl/flash.c | 829
> ------------------------------------------ board/logodl/logodl.c |
> 134 -------
> board/logodl/lowlevel_init.S | 437 ----------------------
> boards.cfg | 1 -
> include/configs/logodl.h | 299 ---------------
> 8 files changed, 1 insertions(+), 1771 deletions(-)
> delete mode 100644 board/logodl/Makefile
> delete mode 100644 board/logodl/config.mk
> delete mode 100644 board/logodl/flash.c
> delete mode 100644 board/logodl/logodl.c
> delete mode 100644 board/logodl/lowlevel_init.S
> delete mode 100644 include/configs/logodl.h
>
> diff --git a/CREDITS b/CREDITS
> index 2c3553e..7670af9 100644
> --- a/CREDITS
> +++ b/CREDITS
> @@ -200,10 +200,6 @@ N: Andreas Heppel
> E: aheppel at sysgo.de
> D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!]
>
> -N: August Hoeraendl
> -E: august.hoerandl at gmx.at
> -D: Support for the logodl board (PXA2xx)
> -
> N: Josh Huber
> E: huber at alum.wpi.edu
> D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series.
> @@ -441,7 +437,7 @@ D: Support for Matrix Vision boards
> (MVBLM7/MVBC_P/MVSMR)
>
> N: Robert Schwebel
> E: r.schwebel at pengutronix.de
> -D: Support for csb226, logodl and innokom boards (PXA2xx)
> +D: Support for csb226 and innokom boards (PXA2xx)
>
> N: Aaron Sells
> E: sellsa at embeddedplanet.com
> diff --git a/board/logodl/Makefile b/board/logodl/Makefile
> deleted file mode 100644
> index 0795b6b..0000000
> --- a/board/logodl/Makefile
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -#
> -# (C) Copyright 2000-2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# See file CREDITS for list of people who contributed to this
> -# project.
> -#
> -# This program is free software; you can redistribute it and/or
> -# modify it under the terms of the GNU General Public License as
> -# published by the Free Software Foundation; either version 2 of
> -# the License, or (at your option) any later version.
> -#
> -# This program is distributed in the hope that it will be useful,
> -# but WITHOUT ANY WARRANTY; without even the implied warranty of
> -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> -# GNU General Public License for more details.
> -#
> -# You should have received a copy of the GNU General Public License
> -# along with this program; if not, write to the Free Software
> -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> -# MA 02111-1307 USA
> -#
> -
> -include $(TOPDIR)/config.mk
> -
> -LIB = $(obj)lib$(BOARD).a
> -
> -COBJS := logodl.o flash.o
> -SOBJS := lowlevel_init.o
> -
> -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> -OBJS := $(addprefix $(obj),$(COBJS))
> -SOBJS := $(addprefix $(obj),$(SOBJS))
> -
> -$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
> -
> -clean:
> - rm -f $(SOBJS) $(OBJS)
> -
> -distclean: clean
> - rm -f $(LIB) core *.bak $(obj).depend
> -
> -#########################################################################
> -
> -# defines $(obj).depend target
> -include $(SRCTREE)/rules.mk
> -
> -sinclude $(obj).depend
> -
> -#########################################################################
> diff --git a/board/logodl/config.mk b/board/logodl/config.mk
> deleted file mode 100644
> index 76c382d..0000000
> --- a/board/logodl/config.mk
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -#
> -# Linux-Kernel is expected to be at c000'8000, entry c000'8000
> -#
> -# we load ourself to c170'0000, the upper 1 MB of second bank
> -#
> -# download areas is c800'0000
> -#
> -
> -#TEXT_BASE = 0
> -
> -# FIXME: armboot does only work correctly when being compiled
> -# # for the addresses _after_ relocation to RAM!! Otherwhise the
> -# # .bss segment is assumed in flash...
> -#
> -TEXT_BASE = 0x083E0000
> diff --git a/board/logodl/flash.c b/board/logodl/flash.c
> deleted file mode 100644
> index 593943f..0000000
> --- a/board/logodl/flash.c
> +++ /dev/null
> @@ -1,829 +0,0 @@
> -/*
> - * (C) 2000 Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> - * (C) 2003 August Hoeraendl, Logotronic GmbH
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#undef CONFIG_FLASH_16BIT
> -
> -#include <common.h>
> -
> -#define FLASH_BANK_SIZE 0x1000000
> -#define MAIN_SECT_SIZE 0x20000 /* 2x64k = 128k per sector */
> -
> -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH
> chips */ -
> -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
> - * has nothing to do with the flash chip being 8-bit or 16-bit.
> - */
> -#ifdef CONFIG_FLASH_16BIT
> -typedef unsigned short FLASH_PORT_WIDTH;
> -typedef volatile unsigned short FLASH_PORT_WIDTHV;
> -
> -#define FLASH_ID_MASK 0xFFFF
> -#else
> -typedef unsigned long FLASH_PORT_WIDTH;
> -typedef volatile unsigned long FLASH_PORT_WIDTHV;
> -
> -#define FLASH_ID_MASK 0xFFFFFFFF
> -#endif
> -
> -#define FPW FLASH_PORT_WIDTH
> -#define FPWV FLASH_PORT_WIDTHV
> -
> -#define ORMASK(size) ((-size) & OR_AM_MSK)
> -
> -/*-----------------------------------------------------------------------
> - * Functions
> - */
> -static ulong flash_get_size(FPWV *addr, flash_info_t *info);
> -static void flash_reset(flash_info_t *info);
> -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
> -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
> -#define write_word(in, de, da) write_word_amd(in, de, da)
> -static void flash_get_offsets(ulong base, flash_info_t *info);
> -#ifdef CONFIG_SYS_FLASH_PROTECTION
> -static void flash_sync_real_protect(flash_info_t *info);
> -#endif
> -
> -/*-----------------------------------------------------------------------
> - * flash_init()
> - *
> - * sets up flash_info and returns size of FLASH (bytes)
> - */
> -ulong flash_init(void)
> -{
> - int i, j;
> - ulong size = 0;
> -
> - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
> - {
> - ulong flashbase = 0;
> - flash_info[i].flash_id =
> - (FLASH_MAN_AMD & FLASH_VENDMASK) |
> - (FLASH_AM640U & FLASH_TYPEMASK);
> - flash_info[i].size = FLASH_BANK_SIZE;
> - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
> - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
> - switch (i)
> - {
> - case 0:
> - flashbase = PHYS_FLASH_1;
> - break;
> - case 1:
> - flashbase = PHYS_FLASH_2;
> - break;
> - default:
> - panic("configured too many flash banks!\n");
> - break;
> - }
> - for (j = 0; j < flash_info[i].sector_count; j++)
> - {
> - flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
> - }
> - size += flash_info[i].size;
> - }
> -
> - /* Protect monitor and environment sectors
> - */
> - flash_protect(FLAG_PROTECT_SET,
> - CONFIG_SYS_FLASH_BASE,
> - CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
> - &flash_info[0]);
> -
> - flash_protect(FLAG_PROTECT_SET,
> - CONFIG_ENV_ADDR,
> - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
> - &flash_info[0]);
> -
> - return size;
> -}
> -
> -/*-----------------------------------------------------------------------
> - */
> -static void flash_reset(flash_info_t *info)
> -{
> - FPWV *base = (FPWV *)(info->start[0]);
> -
> - /* Put FLASH back in read mode */
> - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
> - *base = (FPW)0x00FF00FF; /* Intel Read Mode */
> - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
> - *base = (FPW)0x00F000F0; /* AMD Read Mode */
> -}
> -
> -/*-----------------------------------------------------------------------
> - */
> -static void flash_get_offsets (ulong base, flash_info_t *info)
> -{
> - int i;
> -
> - /* set up sector start address table */
> - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
> - && (info->flash_id & FLASH_BTYPE)) {
> - int bootsect_size; /* number of bytes/boot sector */
> - int sect_size; /* number of bytes/regular sector */
> -
> - bootsect_size = 0x00002000 * (sizeof(FPW)/2);
> - sect_size = 0x00010000 * (sizeof(FPW)/2);
> -
> - /* set sector offsets for bottom boot block type */
> - for (i = 0; i < 8; ++i) {
> - info->start[i] = base + (i * bootsect_size);
> - }
> - for (i = 8; i < info->sector_count; i++) {
> - info->start[i] = base + ((i - 7) * sect_size);
> - }
> - }
> - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
> - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
> -
> - int sect_size; /* number of bytes/sector */
> -
> - sect_size = 0x00010000 * (sizeof(FPW)/2);
> -
> - /* set up sector start address table (uniform sector type) */
> - for( i = 0; i < info->sector_count; i++ )
> - info->start[i] = base + (i * sect_size);
> - }
> -}
> -
> -/*-----------------------------------------------------------------------
> - */
> -
> -void flash_print_info (flash_info_t *info)
> -{
> - int i;
> - uchar *boottype;
> - uchar *bootletter;
> - uchar *fmt;
> - uchar botbootletter[] = "B";
> - uchar topbootletter[] = "T";
> - uchar botboottype[] = "bottom boot sector";
> - uchar topboottype[] = "top boot sector";
> -
> - if (info->flash_id == FLASH_UNKNOWN) {
> - printf ("missing or unknown FLASH type\n");
> - return;
> - }
> -
> - switch (info->flash_id & FLASH_VENDMASK) {
> - case FLASH_MAN_AMD: printf ("AMD "); break;
> - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
> - case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
> - case FLASH_MAN_SST: printf ("SST "); break;
> - case FLASH_MAN_STM: printf ("STM "); break;
> - case FLASH_MAN_INTEL: printf ("INTEL "); break;
> - default: printf ("Unknown Vendor "); break;
> - }
> -
> - /* check for top or bottom boot, if it applies */
> - if (info->flash_id & FLASH_BTYPE) {
> - boottype = botboottype;
> - bootletter = botbootletter;
> - }
> - else {
> - boottype = topboottype;
> - bootletter = topbootletter;
> - }
> -
> - switch (info->flash_id & FLASH_TYPEMASK) {
> - case FLASH_AM640U:
> - fmt = "29LV641D (64 Mbit, uniform sectors)\n";
> - break;
> - case FLASH_28F800C3B:
> - case FLASH_28F800C3T:
> - fmt = "28F800C3%s (8 Mbit, %s)\n";
> - break;
> - case FLASH_INTEL800B:
> - case FLASH_INTEL800T:
> - fmt = "28F800B3%s (8 Mbit, %s)\n";
> - break;
> - case FLASH_28F160C3B:
> - case FLASH_28F160C3T:
> - fmt = "28F160C3%s (16 Mbit, %s)\n";
> - break;
> - case FLASH_INTEL160B:
> - case FLASH_INTEL160T:
> - fmt = "28F160B3%s (16 Mbit, %s)\n";
> - break;
> - case FLASH_28F320C3B:
> - case FLASH_28F320C3T:
> - fmt = "28F320C3%s (32 Mbit, %s)\n";
> - break;
> - case FLASH_INTEL320B:
> - case FLASH_INTEL320T:
> - fmt = "28F320B3%s (32 Mbit, %s)\n";
> - break;
> - case FLASH_28F640C3B:
> - case FLASH_28F640C3T:
> - fmt = "28F640C3%s (64 Mbit, %s)\n";
> - break;
> - case FLASH_INTEL640B:
> - case FLASH_INTEL640T:
> - fmt = "28F640B3%s (64 Mbit, %s)\n";
> - break;
> - default:
> - fmt = "Unknown Chip Type\n";
> - break;
> - }
> -
> - printf (fmt, bootletter, boottype);
> -
> - printf (" Size: %ld MB in %d Sectors\n",
> - info->size >> 20,
> - info->sector_count);
> -
> - printf (" Sector Start Addresses:");
> -
> - for (i=0; i<info->sector_count; ++i) {
> - if ((i % 5) == 0) {
> - printf ("\n ");
> - }
> -
> - printf (" %08lX%s", info->start[i],
> - info->protect[i] ? " (RO)" : " ");
> - }
> -
> - printf ("\n");
> -}
> -
> -/*-----------------------------------------------------------------------
> - */
> -
> -/*
> - * The following code cannot be run from FLASH!
> - */
> -
> -ulong flash_get_size (FPWV *addr, flash_info_t *info)
> -{
> - /* Write auto select command: read Manufacturer ID */
> -
> - /* Write auto select command sequence and test FLASH answer */
> - addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
> - addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */
> - addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */
> -
> - /* The manufacturer codes are only 1 byte, so just use 1 byte.
> - * This works for any bus width and any FLASH device width.
> - */
> - switch (addr[0] & 0xff) {
> -
> - case (uchar)AMD_MANUFACT:
> - info->flash_id = FLASH_MAN_AMD;
> - break;
> -
> - case (uchar)INTEL_MANUFACT:
> - info->flash_id = FLASH_MAN_INTEL;
> - break;
> -
> - default:
> - info->flash_id = FLASH_UNKNOWN;
> - info->sector_count = 0;
> - info->size = 0;
> - break;
> - }
> -
> - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
> - if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
> -
> - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
> - info->flash_id += FLASH_AM640U;
> - info->sector_count = 128;
> - info->size = 0x00800000 * (sizeof(FPW)/2);
> - break; /* => 8 or 16 MB */
> -
> - case (FPW)INTEL_ID_28F800C3B:
> - info->flash_id += FLASH_28F800C3B;
> - info->sector_count = 23;
> - info->size = 0x00100000 * (sizeof(FPW)/2);
> - break; /* => 1 or 2 MB */
> -
> - case (FPW)INTEL_ID_28F800B3B:
> - info->flash_id += FLASH_INTEL800B;
> - info->sector_count = 23;
> - info->size = 0x00100000 * (sizeof(FPW)/2);
> - break; /* => 1 or 2 MB */
> -
> - case (FPW)INTEL_ID_28F160C3B:
> - info->flash_id += FLASH_28F160C3B;
> - info->sector_count = 39;
> - info->size = 0x00200000 * (sizeof(FPW)/2);
> - break; /* => 2 or 4 MB */
> -
> - case (FPW)INTEL_ID_28F160B3B:
> - info->flash_id += FLASH_INTEL160B;
> - info->sector_count = 39;
> - info->size = 0x00200000 * (sizeof(FPW)/2);
> - break; /* => 2 or 4 MB */
> -
> - case (FPW)INTEL_ID_28F320C3B:
> - info->flash_id += FLASH_28F320C3B;
> - info->sector_count = 71;
> - info->size = 0x00400000 * (sizeof(FPW)/2);
> - break; /* => 4 or 8 MB */
> -
> - case (FPW)INTEL_ID_28F320B3B:
> - info->flash_id += FLASH_INTEL320B;
> - info->sector_count = 71;
> - info->size = 0x00400000 * (sizeof(FPW)/2);
> - break; /* => 4 or 8 MB */
> -
> - case (FPW)INTEL_ID_28F640C3B:
> - info->flash_id += FLASH_28F640C3B;
> - info->sector_count = 135;
> - info->size = 0x00800000 * (sizeof(FPW)/2);
> - break; /* => 8 or 16 MB */
> -
> - case (FPW)INTEL_ID_28F640B3B:
> - info->flash_id += FLASH_INTEL640B;
> - info->sector_count = 135;
> - info->size = 0x00800000 * (sizeof(FPW)/2);
> - break; /* => 8 or 16 MB */
> -
> - default:
> - info->flash_id = FLASH_UNKNOWN;
> - info->sector_count = 0;
> - info->size = 0;
> - return (0); /* => no or unknown flash */
> - }
> -
> - flash_get_offsets((ulong)addr, info);
> -
> - /* Put FLASH back in read mode */
> - flash_reset(info);
> -
> - return (info->size);
> -}
> -
> -#ifdef CONFIG_SYS_FLASH_PROTECTION
> -/*-----------------------------------------------------------------------
> - */
> -
> -static void flash_sync_real_protect(flash_info_t *info)
> -{
> - FPWV *addr = (FPWV *)(info->start[0]);
> - FPWV *sect;
> - int i;
> -
> - switch (info->flash_id & FLASH_TYPEMASK) {
> - case FLASH_28F800C3B:
> - case FLASH_28F800C3T:
> - case FLASH_28F160C3B:
> - case FLASH_28F160C3T:
> - case FLASH_28F320C3B:
> - case FLASH_28F320C3T:
> - case FLASH_28F640C3B:
> - case FLASH_28F640C3T:
> - /* check for protected sectors */
> - *addr = (FPW)0x00900090;
> - for (i = 0; i < info->sector_count; i++) {
> - /* read sector protection at sector address, (A7 .. A0) = 0x02.
> - * D0 = 1 for each device if protected.
> - * If at least one device is protected the sector is marked
> - * protected, but mixed protected and unprotected devices
> - * within a sector should never happen.
> - */
> - sect = (FPWV *)(info->start[i]);
> - info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0;
> - }
> -
> - /* Put FLASH back in read mode */
> - flash_reset(info);
> - break;
> -
> - case FLASH_AM640U:
> - default:
> - /* no hardware protect that we support */
> - break;
> - }
> -}
> -#endif
> -
> -/*-----------------------------------------------------------------------
> - */
> -
> -int flash_erase (flash_info_t *info, int s_first, int s_last)
> -{
> - FPWV *addr;
> - int flag, prot, sect;
> - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
> - ulong start, now, last;
> - int rcode = 0;
> -
> - if ((s_first < 0) || (s_first > s_last)) {
> - if (info->flash_id == FLASH_UNKNOWN) {
> - printf ("- missing\n");
> - } else {
> - printf ("- no sectors to erase\n");
> - }
> - return 1;
> - }
> -
> - switch (info->flash_id & FLASH_TYPEMASK) {
> - case FLASH_INTEL800B:
> - case FLASH_INTEL160B:
> - case FLASH_INTEL320B:
> - case FLASH_INTEL640B:
> - case FLASH_28F800C3B:
> - case FLASH_28F160C3B:
> - case FLASH_28F320C3B:
> - case FLASH_28F640C3B:
> - case FLASH_AM640U:
> - break;
> - case FLASH_UNKNOWN:
> - default:
> - printf ("Can't erase unknown flash type %08lx - aborted\n",
> - info->flash_id);
> - return 1;
> - }
> -
> - prot = 0;
> - for (sect=s_first; sect<=s_last; ++sect) {
> - if (info->protect[sect]) {
> - prot++;
> - }
> - }
> -
> - if (prot) {
> - printf ("- Warning: %d protected sectors will not be erased!\n",
> - prot);
> - } else {
> - printf ("\n");
> - }
> -
> - start = get_timer(0);
> - last = start;
> -
> - /* Start erase on unprotected sectors */
> - for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
> -
> - if (info->protect[sect] != 0) /* protected, skip it */
> - continue;
> -
> - /* Disable interrupts which might cause a timeout here */
> - flag = disable_interrupts();
> -
> - addr = (FPWV *)(info->start[sect]);
> - if (intel) {
> - *addr = (FPW)0x00500050; /* clear status register */
> - *addr = (FPW)0x00200020; /* erase setup */
> - *addr = (FPW)0x00D000D0; /* erase confirm */
> - }
> - else {
> - /* must be AMD style if not Intel */
> - FPWV *base; /* first address in bank */
> -
> - base = (FPWV *)(info->start[0]);
> - base[0x0555] = (FPW)0x00AA00AA; /* unlock */
> - base[0x02AA] = (FPW)0x00550055; /* unlock */
> - base[0x0555] = (FPW)0x00800080; /* erase mode */
> - base[0x0555] = (FPW)0x00AA00AA; /* unlock */
> - base[0x02AA] = (FPW)0x00550055; /* unlock */
> - *addr = (FPW)0x00300030; /* erase sector */
> - }
> -
> - /* re-enable interrupts if necessary */
> - if (flag)
> - enable_interrupts();
> -
> - /* wait at least 50us for AMD, 80us for Intel.
> - * Let's wait 1 ms.
> - */
> - udelay (1000);
> -
> - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
> - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
> - printf ("Timeout\n");
> -
> - if (intel) {
> - /* suspend erase */
> - *addr = (FPW)0x00B000B0;
> - }
> -
> - flash_reset(info); /* reset to read mode */
> - rcode = 1; /* failed */
> - break;
> - }
> -
> - /* show that we're waiting */
> - if ((now - last) > 1000) { /* every second */
> - putc ('.');
> - last = now;
> - }
> - }
> -
> - flash_reset(info); /* reset to read mode */
> - }
> -
> - printf (" done\n");
> - return rcode;
> -}
> -
> -/*-----------------------------------------------------------------------
> - * Copy memory to flash, returns:
> - * 0 - OK
> - * 1 - write timeout
> - * 2 - Flash not erased
> - */
> -int bad_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
> -{
> - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX
> */ - int bytes; /* number of bytes to program in current word */
-
> int left; /* number of bytes left to program */
> - int i, res;
> -
> - for (left = cnt, res = 0;
> - left > 0 && res == 0;
> - addr += sizeof(data), left -= sizeof(data) - bytes) {
> -
> - bytes = addr & (sizeof(data) - 1);
> - addr &= ~(sizeof(data) - 1);
> -
> - /* combine source and destination data so can program
> - * an entire word of 16 or 32 bits
> - */
> - for (i = 0; i < sizeof(data); i++) {
> - data <<= 8;
> - if (i < bytes || i - bytes >= left )
> - data += *((uchar *)addr + i);
> - else
> - data += *src++;
> - }
> -
> - /* write one word to the flash */
> - switch (info->flash_id & FLASH_VENDMASK) {
> - case FLASH_MAN_AMD:
> - res = write_word_amd(info, (FPWV *)addr, data);
> - break;
> - case FLASH_MAN_INTEL:
> - res = write_word_intel(info, (FPWV *)addr, data);
> - break;
> - default:
> - /* unknown flash type, error! */
> - printf ("missing or unknown FLASH type\n");
> - res = 1; /* not really a timeout, but gives error */
> - break;
> - }
> - }
> -
> - return (res);
> -}
> -
> -/**
> - * write_buf: - Copy memory to flash.
> - *
> - * @param info:
> - * @param src: source of copy transaction
> - * @param addr: where to copy to
> - * @param cnt: number of bytes to copy
> - *
> - * @return error code
> - */
> -
> -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
> -{
> - ulong cp, wp;
> - FPW data;
> - int l;
> - int i, rc;
> -
> - wp = (addr & ~1); /* get lower word aligned address */
> -
> - /*
> - * handle unaligned start bytes
> - */
> - if ((l = addr - wp) != 0) {
> - data = 0;
> - for (i=0, cp=wp; i<l; ++i, ++cp) {
> - data = (data >> 8) | (*(uchar *)cp << 8);
> - }
> - for (; i<2 && cnt>0; ++i) {
> - data = (data >> 8) | (*src++ << 8);
> - --cnt;
> - ++cp;
> - }
> - for (; cnt==0 && i<2; ++i, ++cp) {
> - data = (data >> 8) | (*(uchar *)cp << 8);
> - }
> -
> - if ((rc = write_word(info, wp, data)) != 0) {
> - return (rc);
> - }
> - wp += 2;
> - }
> -
> - /*
> - * handle word aligned part
> - */
> - while (cnt >= 2) {
> - /* data = *((vushort*)src); */
> - data = *((FPW*)src);
> - if ((rc = write_word(info, wp, data)) != 0) {
> - return (rc);
> - }
> - src += sizeof(FPW);
> - wp += sizeof(FPW);
> - cnt -= sizeof(FPW);
> - }
> -
> - if (cnt == 0) return ERR_OK;
> -
> - /*
> - * handle unaligned tail bytes
> - */
> - data = 0;
> - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
> - data = (data >> 8) | (*src++ << 8);
> - --cnt;
> - }
> - for (; i<2; ++i, ++cp) {
> - data = (data >> 8) | (*(uchar *)cp << 8);
> - }
> -
> - return write_word(info, wp, data);
> -}
> -
> -
> -/*-----------------------------------------------------------------------
> - * Write a word to Flash for AMD FLASH
> - * A word is 16 or 32 bits, whichever the bus width of the flash bank
> - * (not an individual chip) is.
> - *
> - * returns:
> - * 0 - OK
> - * 1 - write timeout
> - * 2 - Flash not erased
> - */
> -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
> -{
> - ulong start;
> - int flag;
> - int res = 0; /* result, assume success */
> - FPWV *base; /* first address in flash bank */
> -
> - /* Check if Flash is (sufficiently) erased */
> - if ((*dest & data) != data) {
> - return (2);
> - }
> -
> -
> - base = (FPWV *)(info->start[0]);
> - /* Disable interrupts which might cause a timeout here */
> - flag = disable_interrupts();
> -
> - base[0x0555] = (FPW)0x00AA00AA; /* unlock */
> - base[0x02AA] = (FPW)0x00550055; /* unlock */
> - base[0x0555] = (FPW)0x00A000A0; /* selects program mode */
> -
> - *dest = data; /* start programming the data */
> -
> - /* re-enable interrupts if necessary */
> - if (flag)
> - enable_interrupts();
> -
> - start = get_timer (0);
> -
> - /* data polling for D7 */
> - while (res == 0 && (*dest & (FPW)0x00800080) != (data &
> (FPW)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
> {
> - *dest = (FPW)0x00F000F0; /* reset bank */
> - res = 1;
> - }
> - }
> -
> - return (res);
> -}
> -
> -/*-----------------------------------------------------------------------
> - * Write a word to Flash for Intel FLASH
> - * A word is 16 or 32 bits, whichever the bus width of the flash bank
> - * (not an individual chip) is.
> - *
> - * returns:
> - * 0 - OK
> - * 1 - write timeout
> - * 2 - Flash not erased
> - */
> -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
> -{
> - ulong start;
> - int flag;
> - int res = 0; /* result, assume success */
> -
> - /* Check if Flash is (sufficiently) erased */
> - if ((*dest & data) != data) {
> - return (2);
> - }
> -
> - /* Disable interrupts which might cause a timeout here */
> - flag = disable_interrupts();
> -
> - *dest = (FPW)0x00500050; /* clear status register */
> - *dest = (FPW)0x00FF00FF; /* make sure in read mode */
> - *dest = (FPW)0x00400040; /* program setup */
> -
> - *dest = data; /* start programming the data */
> -
> - /* re-enable interrupts if necessary */
> - if (flag)
> - enable_interrupts();
> -
> - start = get_timer (0);
> -
> - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
> - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
> - *dest = (FPW)0x00B000B0; /* Suspend program */
> - res = 1;
> - }
> - }
> -
> - if (res == 0 && (*dest & (FPW)0x00100010))
> - res = 1; /* write failed, time out error is close enough */
> -
> - *dest = (FPW)0x00500050; /* clear status register */
> - *dest = (FPW)0x00FF00FF; /* make sure in read mode */
> -
> - return (res);
> -}
> -
> -#ifdef CONFIG_SYS_FLASH_PROTECTION
> -/*-----------------------------------------------------------------------
> - */
> -int flash_real_protect (flash_info_t * info, long sector, int prot)
> -{
> - int rcode = 0; /* assume success */
> - FPWV *addr; /* address of sector */
> - FPW value;
> -
> - addr = (FPWV *) (info->start[sector]);
> -
> - switch (info->flash_id & FLASH_TYPEMASK) {
> - case FLASH_28F800C3B:
> - case FLASH_28F800C3T:
> - case FLASH_28F160C3B:
> - case FLASH_28F160C3T:
> - case FLASH_28F320C3B:
> - case FLASH_28F320C3T:
> - case FLASH_28F640C3B:
> - case FLASH_28F640C3T:
> - flash_reset (info); /* make sure in read mode */
> - *addr = (FPW) 0x00600060L; /* lock command setup */
> - if (prot)
> - *addr = (FPW) 0x00010001L; /* lock sector */
> - else
> - *addr = (FPW) 0x00D000D0L; /* unlock sector */
> - flash_reset (info); /* reset to read mode */
> -
> - /* now see if it really is locked/unlocked as requested */
> - *addr = (FPW) 0x00900090;
> - /* read sector protection at sector address, (A7 .. A0) = 0x02.
> - * D0 = 1 for each device if protected.
> - * If at least one device is protected the sector is marked
> - * protected, but return failure. Mixed protected and
> - * unprotected devices within a sector should never happen.
> - */
> - value = addr[2] & (FPW) 0x00010001;
> - if (value == 0)
> - info->protect[sector] = 0;
> - else if (value == (FPW) 0x00010001)
> - info->protect[sector] = 1;
> - else {
> - /* error, mixed protected and unprotected */
> - rcode = 1;
> - info->protect[sector] = 1;
> - }
> - if (info->protect[sector] != prot)
> - rcode = 1; /* failed to protect/unprotect as requested */
> -
> - /* reload all protection bits from hardware for now */
> - flash_sync_real_protect (info);
> - break;
> -
> - case FLASH_AM640U:
> - default:
> - /* no hardware protect that we support */
> - info->protect[sector] = prot;
> - break;
> - }
> -
> - return rcode;
> -}
> -#endif
> diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c
> deleted file mode 100644
> index 2562ecc..0000000
> --- a/board/logodl/logodl.c
> +++ /dev/null
> @@ -1,134 +0,0 @@
> -/*
> - * (C) 2002 Kyle Harris <kharris at nexus-tech.net>, Nexus Technologies, Inc.
> - * (C) 2002 Marius Groeger <mgroeger at sysgo.de>, Sysgo GmbH
> - * (C) 2003 Robert Schwebel <r.schwebel at pengutronix.de>, Pengutronix
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#include <common.h>
> -#include <netdev.h>
> -#include <asm/arch/pxa-regs.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/**
> - * board_init: - setup some data structures
> - *
> - * @return: 0 in case of success
> - */
> -
> -int board_init (void)
> -{
> - /* memory and cpu-speed are setup before relocation */
> - /* so we do _nothing_ here */
> -
> - gd->bd->bi_arch_number = MACH_TYPE_LOGODL;
> - gd->bd->bi_boot_params = 0x08000100;
> - gd->bd->bi_baudrate = CONFIG_BAUDRATE;
> -
> - (*((volatile short*)0x14800000)) = 0xff; /* power on eth0 */
> - (*((volatile short*)0x14000000)) = 0xff; /* power on uart */
> -
> - return 0;
> -}
> -
> -
> -/**
> - * dram_init: - setup dynamic RAM
> - *
> - * @return: 0 in case of success
> - */
> -
> -int dram_init (void)
> -{
> - gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> -
> - return 0;
> -}
> -
> -
> -/**
> - * logodl_set_led: - switch LEDs on or off
> - *
> - * @param led: LED to switch (0,1)
> - * @param state: switch on (1) or off (0)
> - */
> -
> -void logodl_set_led(int led, int state)
> -{
> - switch(led) {
> -
> - case 0:
> - if (state==1) {
> - CONFIG_SYS_LED_A_CR = CONFIG_SYS_LED_A_BIT;
> - } else if (state==0) {
> - CONFIG_SYS_LED_A_SR = CONFIG_SYS_LED_A_BIT;
> - }
> - break;
> -
> - case 1:
> - if (state==1) {
> - CONFIG_SYS_LED_B_CR = CONFIG_SYS_LED_B_BIT;
> - } else if (state==0) {
> - CONFIG_SYS_LED_B_SR = CONFIG_SYS_LED_B_BIT;
> - }
> - break;
> - }
> -
> - return;
> -}
> -
> -
> -/**
> - * show_boot_progress: - indicate state of the boot process
> - *
> - * @param status: Status number - see README for details.
> - *
> - * The LOGOTRONIC does only have 2 LEDs, so we switch them on at the most
> - * important states (1, 5, 15).
> - */
> -
> -void show_boot_progress (int status)
> -{
> - if (status < -32) status = -1; /* let things compatible */
> - /*
> - switch(status) {
> - case 1: logodl_set_led(0,1); break;
> - case 5: logodl_set_led(1,1); break;
> - case 15: logodl_set_led(2,1); break;
> - }
> - */
> - logodl_set_led(0, (status & 1)==1);
> - logodl_set_led(1, (status & 2)==2);
> -
> - return;
> -}
> -
> -#ifdef CONFIG_CMD_NET
> -int board_eth_init(bd_t *bis)
> -{
> - int rc = 0;
> -#ifdef CONFIG_SMC91111
> - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
> -#endif
> - return rc;
> -}
> -#endif
> diff --git a/board/logodl/lowlevel_init.S b/board/logodl/lowlevel_init.S
> deleted file mode 100644
> index 9892430..0000000
> --- a/board/logodl/lowlevel_init.S
> +++ /dev/null
> @@ -1,437 +0,0 @@
> -/*
> - * Most of this taken from Redboot hal_platform_setup.h with cleanup
> - *
> - * NOTE: I haven't clean this up considerably, just enough to get it
> - * running. See hal_platform_setup.h for the source. See
> - * board/cradle/lowlevel_init.S for another PXA250 setup that is
> - * much cleaner.
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -#include <config.h>
> -#include <version.h>
> -#include <asm/arch/pxa-regs.h>
> -
> -DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
> -
> -/* wait for coprocessor write complete */
> - .macro CPWAIT reg
> - mrc p15,0,\reg,c2,c0,0
> - mov \reg,\reg
> - sub pc,pc,#4
> - .endm
> -
> -_TEXT_BASE:
> - .word TEXT_BASE
> -
> -
> -/*
> - * Memory setup
> - */
> -
> -.globl lowlevel_init
> -lowlevel_init:
> -
> - mov r10, lr
> -
> - /* Set up GPIO pins first ----------------------------------------- */
> -
> - ldr r0, =GPSR0
> - ldr r1, =CONFIG_SYS_GPSR0_VAL
> - str r1, [r0]
> -
> - ldr r0, =GPSR1
> - ldr r1, =CONFIG_SYS_GPSR1_VAL
> - str r1, [r0]
> -
> - ldr r0, =GPSR2
> - ldr r1, =CONFIG_SYS_GPSR2_VAL
> - str r1, [r0]
> -
> - ldr r0, =GPCR0
> - ldr r1, =CONFIG_SYS_GPCR0_VAL
> - str r1, [r0]
> -
> - ldr r0, =GPCR1
> - ldr r1, =CONFIG_SYS_GPCR1_VAL
> - str r1, [r0]
> -
> - ldr r0, =GPCR2
> - ldr r1, =CONFIG_SYS_GPCR2_VAL
> - str r1, [r0]
> -
> - ldr r0, =GPDR0
> - ldr r1, =CONFIG_SYS_GPDR0_VAL
> - str r1, [r0]
> -
> - ldr r0, =GPDR1
> - ldr r1, =CONFIG_SYS_GPDR1_VAL
> - str r1, [r0]
> -
> - ldr r0, =GPDR2
> - ldr r1, =CONFIG_SYS_GPDR2_VAL
> - str r1, [r0]
> -
> - ldr r0, =GAFR0_L
> - ldr r1, =CONFIG_SYS_GAFR0_L_VAL
> - str r1, [r0]
> -
> - ldr r0, =GAFR0_U
> - ldr r1, =CONFIG_SYS_GAFR0_U_VAL
> - str r1, [r0]
> -
> - ldr r0, =GAFR1_L
> - ldr r1, =CONFIG_SYS_GAFR1_L_VAL
> - str r1, [r0]
> -
> - ldr r0, =GAFR1_U
> - ldr r1, =CONFIG_SYS_GAFR1_U_VAL
> - str r1, [r0]
> -
> - ldr r0, =GAFR2_L
> - ldr r1, =CONFIG_SYS_GAFR2_L_VAL
> - str r1, [r0]
> -
> - ldr r0, =GAFR2_U
> - ldr r1, =CONFIG_SYS_GAFR2_U_VAL
> - str r1, [r0]
> -
> - ldr r0, =PSSR /* enable GPIO pins */
> - ldr r1, =CONFIG_SYS_PSSR_VAL
> - str r1, [r0]
> -
> -/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
> -/* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */
> -/* str r2, [r3] / need to set MSC1 before trying to write to the HEX
> LEDs */ -/* ldr r2, [r3] / need to read it back to make sure the
value
> latches (see MSC section of manual) */ -/* */
> -/* ldr r1, =LED_BLANK */
> -/* mov r0, #0xFF */
> -/* str r0, [r1] / turn on hex leds */
> -/* */
> -/*loop: */
> -/* */
> -/* ldr r0, =0xB0070001 */
> -/* ldr r1, =_LED */
> -/* str r0, [r1] / hex display */
> -
> -
> - /* ---------------------------------------------------------------- */
> - /* Enable memory interface */
> - /* */
> - /* The sequence below is based on the recommended init steps */
> - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
> - /* Chapter 10. */
> - /* ---------------------------------------------------------------- */
> -
> - /* ---------------------------------------------------------------- */
> - /* Step 1: Wait for at least 200 microsedonds to allow internal */
> - /* clocks to settle. Only necessary after hard reset... */
> - /* FIXME: can be optimized later */
> - /* ---------------------------------------------------------------- */
> -
> - ldr r3, =OSCR /* reset the OS Timer Count to zero */
> - mov r2, #0
> - str r2, [r3]
> - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
> - /* so 0x300 should be plenty */
> -1:
> - ldr r2, [r3]
> - cmp r4, r2
> - bgt 1b
> -
> -mem_init:
> -
> - ldr r1, =MEMC_BASE /* get memory controller base addr. */
> -
> - /* ---------------------------------------------------------------- */
> - /* Step 2a: Initialize Asynchronous static memory controller */
> - /* ---------------------------------------------------------------- */
> -
> - /* MSC registers: timing, bus width, mem type */
> -
> - /* MSC0: nCS(0,1) */
> - ldr r2, =CONFIG_SYS_MSC0_VAL
> - str r2, [r1, #MSC0_OFFSET]
> - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
> - /* that data latches */
> - /* MSC1: nCS(2,3) */
> - ldr r2, =CONFIG_SYS_MSC1_VAL
> - str r2, [r1, #MSC1_OFFSET]
> - ldr r2, [r1, #MSC1_OFFSET]
> -
> - /* MSC2: nCS(4,5) */
> - ldr r2, =CONFIG_SYS_MSC2_VAL
> - str r2, [r1, #MSC2_OFFSET]
> - ldr r2, [r1, #MSC2_OFFSET]
> -
> - /* ---------------------------------------------------------------- */
> - /* Step 2b: Initialize Card Interface */
> - /* ---------------------------------------------------------------- */
> -
> - /* MECR: Memory Expansion Card Register */
> - ldr r2, =CONFIG_SYS_MECR_VAL
> - str r2, [r1, #MECR_OFFSET]
> - ldr r2, [r1, #MECR_OFFSET]
> -
> - /* MCMEM0: Card Interface slot 0 timing */
> - ldr r2, =CONFIG_SYS_MCMEM0_VAL
> - str r2, [r1, #MCMEM0_OFFSET]
> - ldr r2, [r1, #MCMEM0_OFFSET]
> -
> - /* MCMEM1: Card Interface slot 1 timing */
> - ldr r2, =CONFIG_SYS_MCMEM1_VAL
> - str r2, [r1, #MCMEM1_OFFSET]
> - ldr r2, [r1, #MCMEM1_OFFSET]
> -
> - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
> - ldr r2, =CONFIG_SYS_MCATT0_VAL
> - str r2, [r1, #MCATT0_OFFSET]
> - ldr r2, [r1, #MCATT0_OFFSET]
> -
> - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
> - ldr r2, =CONFIG_SYS_MCATT1_VAL
> - str r2, [r1, #MCATT1_OFFSET]
> - ldr r2, [r1, #MCATT1_OFFSET]
> -
> - /* MCIO0: Card Interface I/O Space Timing, slot 0 */
> - ldr r2, =CONFIG_SYS_MCIO0_VAL
> - str r2, [r1, #MCIO0_OFFSET]
> - ldr r2, [r1, #MCIO0_OFFSET]
> -
> - /* MCIO1: Card Interface I/O Space Timing, slot 1 */
> - ldr r2, =CONFIG_SYS_MCIO1_VAL
> - str r2, [r1, #MCIO1_OFFSET]
> - ldr r2, [r1, #MCIO1_OFFSET]
> -
> - /* ---------------------------------------------------------------- */
> - /* Step 2c: Write FLYCNFG FIXME: what's that??? */
> - /* ---------------------------------------------------------------- */
> -
> - /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
> - adr r3, mem_init /* r0 <- current position of code */
> - ldr r2, =mem_init
> - cmp r3, r2 /* skip init if in place */
> - beq initirqs
> -
> -
> - /* ---------------------------------------------------------------- */
> - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
> - /* ---------------------------------------------------------------- */
> -
> - /* Before accessing MDREFR we need a valid DRI field, so we set */
> - /* this to power on defaults + DRI field. */
> -
> - ldr r3, =CONFIG_SYS_MDREFR_VAL
> - ldr r2, =0xFFF
> - and r3, r3, r2
> - ldr r4, =0x03ca4000
> - orr r4, r4, r3
> -
> - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
> - ldr r4, [r1, #MDREFR_OFFSET]
> -
> -
> - /* ---------------------------------------------------------------- */
> - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
> - /* ---------------------------------------------------------------- */
> -
> - /* Initialize SXCNFG register. Assert the enable bits */
> -
> - /* Write SXMRS to cause an MRS command to all enabled banks of */
> - /* synchronous static memory. Note that SXLCR need not be written */
> - /* at this time. */
> -
> - /* FIXME: we use async mode for now */
> -
> -
> - /* ---------------------------------------------------------------- */
> - /* Step 4: Initialize SDRAM */
> - /* ---------------------------------------------------------------- */
> -
> - /* Step 4a: assert MDREFR:K?RUN and configure */
> - /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
> -
> - ldr r4, =CONFIG_SYS_MDREFR_VAL
> - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
> - ldr r4, [r1, #MDREFR_OFFSET]
> -
> - /* Step 4b: de-assert MDREFR:SLFRSH. */
> -
> - bic r4, r4, #(MDREFR_SLFRSH)
> -
> - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
> - ldr r4, [r1, #MDREFR_OFFSET]
> -
> -
> - /* Step 4c: assert MDREFR:E1PIN and E0PIO */
> -
> - orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
> -
> - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
> - ldr r4, [r1, #MDREFR_OFFSET]
> -
> -
> - /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
> - /* configure but not enable each SDRAM partition pair. */
> -
> - ldr r4, =CONFIG_SYS_MDCNFG_VAL
> - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
> -
> - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
> - ldr r4, [r1, #MDCNFG_OFFSET]
> -
> -
> - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
> - /* 100..200 �sec. */
> -
> - ldr r3, =OSCR /* reset the OS Timer Count to zero */
> - mov r2, #0
> - str r2, [r3]
> - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
> - /* so 0x300 should be plenty */
> -1:
> - ldr r2, [r3]
> - cmp r4, r2
> - bgt 1b
> -
> -
> - /* Step 4f: Trigger a number (usually 8) refresh cycles by */
> - /* attempting non-burst read or write accesses to disabled */
> - /* SDRAM, as commonly specified in the power up sequence */
> - /* documented in SDRAM data sheets. The address(es) used */
> - /* for this purpose must not be cacheable. */
> -
> - /* There should 9 writes, since the first write doesn't */
> - /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
> - /* PXA210 Processors Specification Update, */
> - /* Jan 2003, Errata #116, page 30. */
> -
> -
> - ldr r3, =CONFIG_SYS_DRAM_BASE
> - str r2, [r3]
> - str r2, [r3]
> - str r2, [r3]
> - str r2, [r3]
> - str r2, [r3]
> - str r2, [r3]
> - str r2, [r3]
> - str r2, [r3]
> - str r2, [r3]
> -
> - /* Step 4g: Write MDCNFG with enable bits asserted */
> - /* (MDCNFG:DEx set to 1). */
> -
> - ldr r3, [r1, #MDCNFG_OFFSET]
> - orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
> - str r3, [r1, #MDCNFG_OFFSET]
> -
> - /* Step 4h: Write MDMRS. */
> -
> - ldr r2, =CONFIG_SYS_MDMRS_VAL
> - str r2, [r1, #MDMRS_OFFSET]
> -
> -
> - /* We are finished with Intel's memory controller initialisation */
> -
> - /* ---------------------------------------------------------------- */
> - /* Disable (mask) all interrupts at interrupt controller */
> - /* ---------------------------------------------------------------- */
> -
> -initirqs:
> -
> - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
> - ldr r2, =ICLR
> - str r1, [r2]
> -
> - ldr r2, =ICMR /* mask all interrupts at the controller */
> - str r1, [r2]
> -
> -
> - /* ---------------------------------------------------------------- */
> - /* Clock initialisation */
> - /* ---------------------------------------------------------------- */
> -
> -initclks:
> -
> - /* Disable the peripheral clocks, and set the core clock frequency */
> - /* (hard-coding at 398.12MHz for now). */
> -
> - /* Turn Off ALL on-chip peripheral clocks for re-configuration */
> - /* Note: See label 'ENABLECLKS' for the re-enabling */
> - ldr r1, =CKEN
> - mov r2, #0
> - str r2, [r1]
> -
> -
> - /* default value in case no valid rotary switch setting is found */
> - ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
> -
> - /* ... and write the core clock config register */
> - ldr r1, =CCCR
> - str r2, [r1]
> -
> - /* enable the 32Khz oscillator for RTC and PowerManager */
> -/*
> - ldr r1, =OSCC
> - mov r2, #OSCC_OON
> - str r2, [r1]
> -*/
> - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
> - /* has settled. */
> -60:
> - ldr r2, [r1]
> - ands r2, r2, #1
> - beq 60b
> -
> - /* ---------------------------------------------------------------- */
> - /* */
> - /* ---------------------------------------------------------------- */
> -
> - /* Save SDRAM size */
> - ldr r1, =DRAM_SIZE
> - str r8, [r1]
> -
> - /* Interrupt init: Mask all interrupts */
> - ldr r0, =ICMR /* enable no sources */
> - mov r1, #0
> - str r1, [r0]
> -
> - /* FIXME */
> -
> -#ifndef DEBUG
> - /*Disable software and data breakpoints */
> - mov r0,#0
> - mcr p15,0,r0,c14,c8,0 /* ibcr0 */
> - mcr p15,0,r0,c14,c9,0 /* ibcr1 */
> - mcr p15,0,r0,c14,c4,0 /* dbcon */
> -
> - /*Enable all debug functionality */
> - mov r0,#0x80000000
> - mcr p14,0,r0,c10,c0,0 /* dcsr */
> -#endif
> -
> - /* ---------------------------------------------------------------- */
> - /* End lowlevel_init
> */ - /* ----------------------------------------------------------------
> */ -
> -endlowlevel_init:
> -
> - mov pc, lr
> diff --git a/boards.cfg b/boards.cfg
> index 98dfacf..1f0486f 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -58,7 +58,6 @@ cradle arm pxa
> csb226 arm pxa
> delta arm pxa
> innokom arm pxa
> -logodl arm pxa
> lubbock arm pxa
> pleb2 arm pxa
> xaeniax arm pxa
> diff --git a/include/configs/logodl.h b/include/configs/logodl.h
> deleted file mode 100644
> index 0535ee1..0000000
> --- a/include/configs/logodl.h
> +++ /dev/null
> @@ -1,299 +0,0 @@
> -/*
> - * (C) Copyright 2003
> - * Robert Schwebel, Pengutronix, r.schwebel at pengutronix.de.
> - *
> - * Configuration for the Logotronic DL board.
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> - * MA 02111-1307 USA
> - */
> -
> -/*
> - * include/configs/logodl.h - configuration options, board specific
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Configuration Options
> - * (easy to change)
> - */
> -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
> -#define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */
> -
> -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
> - /* for timer/console/ethernet */
> -
> -/* we will never enable dcache, because we have to setup MMU first */
> -#define CONFIG_SYS_NO_DCACHE
> -
> -/*
> - * Hardware drivers
> - */
> -
> -/*
> - * select serial console configuration
> - */
> -#define CONFIG_PXA_SERIAL
> -#define CONFIG_FFUART 1 /* we use FFUART */
> -
> -/* allow to overwrite serial and ethaddr */
> -#define CONFIG_ENV_OVERWRITE
> -
> -#define CONFIG_BAUDRATE 19200
> -#undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */
> -
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -#define CONFIG_BOOTP_BOOTPATH
> -#define CONFIG_BOOTP_GATEWAY
> -#define CONFIG_BOOTP_HOSTNAME
> -
> -
> -/*
> - * Command line configuration.
> - */
> -#define CONFIG_CMD_ASKENV
> -#define CONFIG_CMD_ECHO
> -#define CONFIG_CMD_SAVEENV
> -#define CONFIG_CMD_FLASH
> -#define CONFIG_CMD_MEMORY
> -#define CONFIG_CMD_RUN
> -
> -
> -#define CONFIG_BOOTDELAY 3
> -/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
> -#define CONFIG_BOOTARGS "console=ttyS0,19200"
> -#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
> -#define CONFIG_NETMASK 255.255.255.0
> -#define CONFIG_IPADDR 192.168.1.56
> -#define CONFIG_SERVERIP 192.168.1.2
> -#define CONFIG_BOOTCOMMAND "bootm 0x40000"
> -#define CONFIG_SHOW_BOOT_PROGRESS
> -
> -#define CONFIG_CMDLINE_TAG 1
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -
> -/*
> - * Size of malloc() pool; this lives below the uppermost 128 KiB which are
> - * used for the RAM copy of the uboot code
> - *
> - */
> -#define CONFIG_SYS_MALLOC_LEN (256*1024)
> -
> -#define CONFIG_SYS_LONGHELP /* undef to save memory
*/
> -#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
> -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max
number of
> command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /*
Boot
> Argument Buffer Size */ -
> -#define CONFIG_SYS_MEMTEST_START 0x08000000 /* memtest works on
> */ -#define CONFIG_SYS_MEMTEST_END 0x0800ffff /* 64 KiB
> */ -
> -#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* load kernel to
> this address */ -
> -#define CONFIG_SYS_HZ 1000
> - /* RS: the oscillator is actually 3680130?? */
> -
> -#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock
> to 200/200/100 MHz */ - /* 0101000001 */
> - /* ^^^^^ Memory Speed 99.53 MHz */
> - /* ^^ Run Mode Speed = 2x Mem Speed */
> - /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
> -
> -#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
> -
> - /* valid baudrates */
> -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200
> } -
> -/*
> - * SMSC91C111 Network Card
> - */
> -#if 0
> -#define CONFIG_NET_MULTI
> -#define CONFIG_SMC91111 1
> -#define CONFIG_SMC91111_BASE 0x10000000 /* chip select 4 */
> -#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
> -#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
> -#undef CONFIG_SHOW_ACTIVITY
> -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
> -#endif
> -
> -/*
> - * Stack sizes
> - *
> - * The stack sizes are set up in start.S using the settings below
> - */
> -#define CONFIG_STACKSIZE (128*1024) /* regular stack */
> -#ifdef CONFIG_USE_IRQ
> -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
> -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
> -#endif
> -
> -/*
> - * Physical Memory Map
> - */
> -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of RAM */
> -#define PHYS_SDRAM_1 0x08000000 /* SRAM Bank #1 */
> -#define PHYS_SDRAM_1_SIZE (4*1024*1024) /* 4 MB */
> -
> -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
> -#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
> -#define PHYS_FLASH_SIZE (32*1024*1024) /* 32 MB
*/
> -
> -#define CONFIG_SYS_DRAM_BASE PHYS_SDRAM_1 /* RAM starts here
*/
> -#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE
> -
> -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
> -
> -
> -/*
> - * GPIO settings
> - *
> - * GP?? == FOOBAR is 0/1
> - */
> -
> -#define _BIT0 0x00000001
> -#define _BIT1 0x00000002
> -#define _BIT2 0x00000004
> -#define _BIT3 0x00000008
> -
> -#define _BIT4 0x00000010
> -#define _BIT5 0x00000020
> -#define _BIT6 0x00000040
> -#define _BIT7 0x00000080
> -
> -#define _BIT8 0x00000100
> -#define _BIT9 0x00000200
> -#define _BIT10 0x00000400
> -#define _BIT11 0x00000800
> -
> -#define _BIT12 0x00001000
> -#define _BIT13 0x00002000
> -#define _BIT14 0x00004000
> -#define _BIT15 0x00008000
> -
> -#define _BIT16 0x00010000
> -#define _BIT17 0x00020000
> -#define _BIT18 0x00040000
> -#define _BIT19 0x00080000
> -
> -#define _BIT20 0x00100000
> -#define _BIT21 0x00200000
> -#define _BIT22 0x00400000
> -#define _BIT23 0x00800000
> -
> -#define _BIT24 0x01000000
> -#define _BIT25 0x02000000
> -#define _BIT26 0x04000000
> -#define _BIT27 0x08000000
> -
> -#define _BIT28 0x10000000
> -#define _BIT29 0x20000000
> -#define _BIT30 0x40000000
> -#define _BIT31 0x80000000
> -
> -
> -#define CONFIG_SYS_LED_A_BIT (_BIT18)
> -#define CONFIG_SYS_LED_A_SR GPSR0
> -#define CONFIG_SYS_LED_A_CR GPCR0
> -
> -#define CONFIG_SYS_LED_B_BIT (_BIT16)
> -#define CONFIG_SYS_LED_B_SR GPSR1
> -#define CONFIG_SYS_LED_B_CR GPCR1
> -
> -
> -/* LED A: off, LED B: off */
> -#define CONFIG_SYS_GPSR0_VAL
> (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18) -#define
> CONFIG_SYS_GPSR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25
> +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13) -#define CONFIG_SYS_GPSR2_VAL
> (_BIT14+_BIT15+_BIT16)
> -
> -#define CONFIG_SYS_GPCR0_VAL 0x00000000
> -#define CONFIG_SYS_GPCR1_VAL 0x00000000
> -#define CONFIG_SYS_GPCR2_VAL 0x00000000
> -
> -#define CONFIG_SYS_GPDR0_VAL
> (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18) -#define
> CONFIG_SYS_GPDR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25
> +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13) -#define CONFIG_SYS_GPDR2_VAL
> (_BIT14+_BIT15+_BIT16)
> -
> -#define CONFIG_SYS_GAFR0_L_VAL (_BIT22+_BIT24+_BIT31)
> -#define CONFIG_SYS_GAFR0_U_VAL (_BIT15+_BIT17+_BIT19+\
> - _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
> -#define CONFIG_SYS_GAFR1_L_VAL
> (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\ -
> _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
> -#define CONFIG_SYS_GAFR1_U_VAL
> (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31) -#define
> CONFIG_SYS_GAFR2_L_VAL
> (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\ -
> _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
> -#define CONFIG_SYS_GAFR2_U_VAL (_BIT1)
> -
> -#define CONFIG_SYS_PSSR_VAL (0x20)
> -
> -/*
> - * Memory settings
> - */
> -#define CONFIG_SYS_MSC0_VAL 0x123c2980
> -#define CONFIG_SYS_MSC1_VAL 0x123c2661
> -#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
> -
> -
> -/* no sdram/pcmcia here */
> -#define CONFIG_SYS_MDCNFG_VAL 0x00000000
> -#define CONFIG_SYS_MDREFR_VAL 0x00000000
> -#define CONFIG_SYS_MDREFR_VAL_100 0x00000000
> -#define CONFIG_SYS_MDMRS_VAL 0x00000000
> -
> -/* only SRAM */
> -#define SXCNFG_SETTINGS 0x00000000
> -
> -/*
> - * PCMCIA and CF Interfaces
> - */
> -
> -#define CONFIG_SYS_MECR_VAL 0x00000000
> -#define CONFIG_SYS_MCMEM0_VAL 0x00010504
> -#define CONFIG_SYS_MCMEM1_VAL 0x00010504
> -#define CONFIG_SYS_MCATT0_VAL 0x00010504
> -#define CONFIG_SYS_MCATT1_VAL 0x00010504
> -#define CONFIG_SYS_MCIO0_VAL 0x00004715
> -#define CONFIG_SYS_MCIO1_VAL 0x00004715
> -
> -
> -/*
> - * FLASH and environment organization
> - */
> -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory
> banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max
> number of sectors on one chip */ -
> -/* timeout values are in ticks */
> -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for
> Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ)
> /* Timeout for Flash Write */ -
> -/* FIXME */
> -#define CONFIG_ENV_IS_IN_FLASH 1
> -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr
> of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /*
> Total Size of Environment Sector */ -
> -#endif /* __CONFIG_H */
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