[U-Boot] [PATCH] Disable unused chip-select for DDR controller interleaving

[York Sun]

On Wed, 2010-10-13 at 18:24 +0200, Wolfgang Denk wrote:
> Dear York Sun,
> 
> In message <1286983650-3911-1-git-send-email-yorksun at freescale.com> you wrote:
> > When DDR controller interleaving is eabled and less than all bank (chip-select)
> > interleaving is seletected, the unused chip-select should be disabled.
> ...
> 
> > @@ -1250,16 +1251,20 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
> >  			 * and each controller uses rank interleaving within
> >  			 * itself. Therefore the starting and ending address
> >  			 * on each controller is twice the amount present on
> > -			 * each controller.
> > +			 * each controller.When
> >  			 */
> 
> Seems you wanted to add some comment here, but then forgot it?

Oop. Nice catch. I didn't know how I missed this.

> 
> > @@ -1379,8 +1384,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
> >  			);
> >  
> >  		debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
> > -		set_csn_config(dimm_number, i, ddr, popts, dimm_params);
> > -		set_csn_config_2(i, ddr);
> > +		if (cs_en) {
> > +			set_csn_config(dimm_number, i, ddr, popts, dimm_params);
> > +			set_csn_config_2(i, ddr);
> > +		}
> 
> Would it not be helpful to inform the user that we disabled a memory
> bank? Eventually this wa snot intentional...

I can add a message but maybe not necessary. The only case the CS left
disable is the incomplete interleaving. For example the controller
interleaving is enabled, but the bank interleaving is disabled or less
than all populated CS are interleaving. In these cases, the unused CSs
(or maybe CS'es, my bad English) are not accessible, even enabled. This
patch doesn't change the hardware behavior, but to disable those unused
CS to avoid confusion.

York