[U-Boot] [PATCH] Disable unused chip-select for DDR controller interleaving

York Sun yorksun at freescale.com
Wed Oct 13 19:46:15 CEST 2010


On Wed, 2010-10-13 at 19:41 +0200, Wolfgang Denk wrote:
> Dear York Sun,
> 
> In message <1286988197.5737.6.camel at oslab-l1> you wrote:
> >
> > > Would it not be helpful to inform the user that we disabled a memory
> > > bank? Eventually this wa snot intentional...
> > 
> > I can add a message but maybe not necessary. The only case the CS left
> > disable is the incomplete interleaving. For example the controller
> > interleaving is enabled, but the bank interleaving is disabled or less
> > than all populated CS are interleaving. In these cases, the unused CSs
> > (or maybe CS'es, my bad English) are not accessible, even enabled. This
> > patch doesn't change the hardware behavior, but to disable those unused
> > CS to avoid confusion.
> 
> I understand this.  But I think the conditions that cause such
> behaviour are pretty unusual, and most probably not something that is
> actually intended by the end user - for example, he might have
> installed an incompatible DIMM or such.  It would be nice if he was
> made aware that somthing unusual is going on, so he can double-check
> his configuration.
> 

Points taken. I will add a message for this case.

Thanks.

York





More information about the U-Boot mailing list