[U-Boot] ELF_RELOC causes strange I-cache issues

[Albert ARIBAUD]

Le 21/10/2010 11:51, Heiko Schocher a écrit :
> Hello Albert,
>
> Albert Aribaud wrote:
>> Wolfgang (and others who can/want),
>>
>> Please test this patch; it should add a complete barrier to make
>> sure that all fixups are written to RAM before jumping there, and
>> that no remnants subsist of the old unfixed code in the instruction
>> paths. However, I cannot even do basic testing on it as I have
>> no 1136 board, so I cannot rule out even basic mistakes.
>>
>> When this works I'll do a proper [PATCH].
>>
>> Amicalement,
>> Albert.
>>
>> diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
>> index 8b63192..f49f1de 100644
>> --- a/arch/arm/cpu/arm1136/start.S
>> +++ b/arch/arm/cpu/arm1136/start.S
>> @@ -257,6 +257,11 @@ fixloop:
>>   	add	r2, r2, #4
>>   	cmp	r2, r3
>>   	bne	fixloop
>> +	/* fixups done, cleanup caches if used and prefetch buffer */
>> +	mov	r3, #0
>> +	mcr	p15, 0, r3, c7, c10, 4	/* data synchronization barrier */
>> +	mcr	p15, 0, r3, c7, c5, 0	/* invalidate instruction cache */
>> +	mcr	p15, 0, r3, c7, c5, 4	/* flush prefetch buffer */
>>   #endif
>>   #endif	/* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
>
> Actually I tried an identically patch, but didn;t help :-(
>
> But as reading in the arm manual such a memory barrier should
> not be bad here ...
>
> BTW:
>
> I had a fix for this problem, but I completly not understand
> what it has to do with relocation (if it really is a problem
> introduced through relocation ...), nor why a flush_cache
> helps here, because dcache is off and only icache is on ...

Still, this is a clue.

> +       flush_cache(0, 0);

This amounts to calling arm1136_flush_cache.

Wolfgang/other testers, can you do the following three tests?

1. Replace the three mcr instructions I added in my patch with this single

	mcr     p15, 0, r1, c7, c5, 0 /* invalidate I-cache */

2. Replace the three mcr instructions I added in my patch with this single

	mcr     p15, 0, r1, c7, c14, 0 /* invalidate D cache */

3. Replace the three mcr instructions I added in my patch with these two

	mcr     p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
	mcr     p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
	
> Maybe Icache flush dosen;t work because the "ARM1136 Errata 411920
> Invalidate Instruction Cache operation can fail" interferes here?

My ARM account seems to not allow me to get these errata from them. I've 
just asked for extended access, but meanwhile, is a summary of this 
errata freely available?

Amicalement,
-- 
Albert.