[U-Boot] [PATCH 1/5] mpc83xx/pcie: make it compile with PCIE2 unconfigured

[Ilya Yanok]

MPC8308 has only one PCIE host controller so we want it to compile
without CONFIG_SYS_PCIE2_CFG_{BASE,SIZE} defined.

Signed-off-by: Ilya Yanok <yanok at emcraft.com>
---
 arch/powerpc/cpu/mpc83xx/pcie.c |   47 ++++++++++++++++++++++++++++----------
 1 files changed, 34 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 77f8906..abb7a49 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -28,7 +28,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_SIZE)
 #define PCIE_MAX_BUSES 2
+#else
+#define PCIE_MAX_BUSES 1
+#endif
 
 #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
 
@@ -93,6 +97,18 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 	static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
 	struct pci_controller *hose = &pcie_hose[bus];
 	int i;
+	unsigned int *cfg_addr;
+
+	if (bus == 0) {
+		cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE;
+	} else {
+#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_SIZE)
+		cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE;
+#else
+		printf("Second PCIE host controller not configured!\n");
+		return;
+#endif
+	}
 
 	/*
 	 * There are no spare BATs to remap all PCI-E windows for U-Boot, so
@@ -124,10 +140,7 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 	hose->first_busno = pci_last_busno() + 1;
 	hose->last_busno = 0xff;
 
-	if (bus == 0)
-		hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE;
-	else
-		hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE;
+	hose->cfg_addr = cfg_addr;
 
 	pci_set_ops(hose,
 			pcie_read_config_byte,
@@ -170,6 +183,21 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
 	unsigned int tar;
 	u16 reg16;
 	int i;
+	u32 cfg_size;
+	u32 cfg_base;
+
+	if (bus) {
+#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_SIZE)
+		cfg_size = CONFIG_SYS_PCIE2_SIZE;
+		cfg_base = CONFIG_SYS_PCIE2_CFG_BASE;
+#else
+		printf("Second PCIE host controller not configured!\n");
+		return;
+#endif
+	} else {
+		cfg_size = CONFIG_SYS_PCIE1_CFG_SIZE;
+		cfg_base = CONFIG_SYS_PCIE1_CFG_BASE;
+	}
 
 	/* Enable pex csb bridge inbound & outbound transactions */
 	out_le32(&pex->bridge.pex_csb_ctrl,
@@ -182,15 +210,8 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
 		PEX_CSB_OBCTRL_CFGWE);
 
 	out_win = &pex->bridge.pex_outbound_win[0];
-	if (bus) {
-		out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
-			CONFIG_SYS_PCIE2_CFG_SIZE);
-		out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE);
-	} else {
-		out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
-			CONFIG_SYS_PCIE1_CFG_SIZE);
-		out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE);
-	}
+	out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | cfg_size);
+	out_le32(&out_win->bar, cfg_base);
 	out_le32(&out_win->tarl, 0);
 	out_le32(&out_win->tarh, 0);
 
-- 
1.6.2.5