[U-Boot] [PATCH v3] ppc4xx/fdt/flash: Change fdt_fixup_nor_flash_node() to not rely on cs size
Stefan Roese
sr at denx.de
Tue Sep 21 17:31:28 CEST 2010
This patch changes the behaviour of the fdt_fixup_nor_flash_node()
function. Now it doesn't patch the size of the "reg" property with the
chip-select size, but with the size returned from the new function
flash_get_bank_size(). This function will return per weak default the
flash size of the bank (bank = chip-select numer) detected by the flash
driver. If this does not fit your needs, this function may be overridden
by a board specific one.
For this the parameters needed to be changed. So I intentionally squashed
the PPC4xx stuff using this routine into this patch. Otherwise it would
not be git-bisectable anymore.
The board specific function for the AMCC/APM Ebony eval board is now
included in this patch version.
Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Gerald Van Baren <vanbaren at cideas.com>
Cc: Wolfgang Denk <wd at denx.de>
ppc4xx: Add board specific function to return the detected flash size
This function will be called to fixup size of the "reg" property of the
NOR flash device tree nodes. Ebony can't use the weak default, since
it has a special chip-select to bank-number binding.
Signed-off-by: Stefan Roese <sr at denx.de>
---
v3:
- Removed CONFIG_FDT_FIXUP_NOR_FLASH_SIZE from acadia_nand target
since it has no NOR flash at all and compiling fails with
flash_info undefined.
v2:
- Ebony's board specific function squashed into this patch
arch/powerpc/cpu/ppc4xx/fdt.c | 10 ++++----
board/amcc/ebony/flash.c | 31 +++++++++++++++++++++++++
common/fdt_support.c | 51 +++++++++++++++++++++++++++++++++--------
include/configs/acadia.h | 8 +++++-
include/fdt_support.h | 2 +-
5 files changed, 85 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c
index 15a184b..e99b2b0 100644
--- a/arch/powerpc/cpu/ppc4xx/fdt.c
+++ b/arch/powerpc/cpu/ppc4xx/fdt.c
@@ -59,14 +59,14 @@ void __ft_board_setup(void *blob, bd_t *bd)
*p++ = 0;
*p++ = bxcr & EBC_BXCR_BAS_MASK;
*p++ = EBC_BXCR_BANK_SIZE(bxcr);
+ }
+ }
+
#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
- /* Try to update reg property in nor flash node too */
- fdt_fixup_nor_flash_size(blob, i,
- EBC_BXCR_BANK_SIZE(bxcr));
+ /* Update reg property in all nor flash nodes too */
+ fdt_fixup_nor_flash_size(blob);
#endif
- }
- }
/* Some 405 PPC's have EBC as direct PLB child in the dts */
if (fdt_path_offset(blob, ebc_path) < 0)
diff --git a/board/amcc/ebony/flash.c b/board/amcc/ebony/flash.c
index 8fe3ba1..79d2c4c 100644
--- a/board/amcc/ebony/flash.c
+++ b/board/amcc/ebony/flash.c
@@ -34,6 +34,7 @@
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
+#include <asm/io.h>
#undef DEBUG
#ifdef DEBUG
@@ -71,6 +72,36 @@ static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+/*
+ * Override the weak default mapping function with a board specific one
+ */
+u32 flash_get_bank_size(int cs, int idx)
+{
+ u8 reg = in_8((void *)CONFIG_SYS_FPGA_BASE);
+
+ if ((reg & BOOT_SMALL_FLASH) && !(reg & FLASH_ONBD_N)) {
+ /*
+ * cs0: small flash (512KiB)
+ * cs2: 2 * big flash (2 * 2MiB)
+ */
+ if (cs == 0)
+ return flash_info[2].size;
+ if (cs == 2)
+ return flash_info[0].size + flash_info[1].size;
+ } else {
+ /*
+ * cs0: 2 * big flash (2 * 2MiB)
+ * cs2: small flash (512KiB)
+ */
+ if (cs == 0)
+ return flash_info[0].size + flash_info[1].size;
+ if (cs == 2)
+ return flash_info[2].size;
+ }
+
+ return 0;
+}
+
unsigned long flash_init(void)
{
unsigned long total_b = 0;
diff --git a/common/fdt_support.c b/common/fdt_support.c
index aef4fe2..6f32e3f 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -591,11 +591,30 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) {
#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
/*
+ * Provide a weak default function to return the flash bank size.
+ * There might be multiple non-identical flash chips connected to one
+ * chip-select, so we need to pass an index as well.
+ */
+u32 __flash_get_bank_size(int cs, int idx)
+{
+ extern flash_info_t flash_info[];
+
+ /*
+ * As default, a simple 1:1 mapping is provided. Boards with
+ * a different mapping need to supply a board specific mapping
+ * routine.
+ */
+ return flash_info[cs].size;
+}
+u32 flash_get_bank_size(int cs, int idx)
+ __attribute__((weak, alias("__flash_get_bank_size")));
+
+/*
* This function can be used to update the size in the "reg" property
- * of the NOR FLASH device nodes. This is necessary for boards with
+ * of all NOR FLASH device nodes. This is necessary for boards with
* non-fixed NOR FLASH sizes.
*/
-int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size)
+int fdt_fixup_nor_flash_size(void *blob)
{
char compat[][16] = { "cfi-flash", "jedec-flash" };
int off;
@@ -607,19 +626,31 @@ int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size)
for (i = 0; i < 2; i++) {
off = fdt_node_offset_by_compatible(blob, -1, compat[i]);
while (off != -FDT_ERR_NOTFOUND) {
+ int idx;
+
/*
- * Found one compatible node, now check if this one
- * has the correct CS
+ * Found one compatible node, so fixup the size
+ * int its reg properties
*/
prop = fdt_get_property_w(blob, off, "reg", &len);
if (prop) {
+ int tuple_size = 3 * sizeof(reg);
+
+ /*
+ * There might be multiple reg-tuples,
+ * so loop through them all
+ */
+ len /= tuple_size;
reg = (u32 *)&prop->data[0];
- if (reg[0] == cs) {
- reg[2] = size;
+ for (idx = 0; idx < len; idx++) {
+ /*
+ * Update size in reg property
+ */
+ reg[2] = flash_get_bank_size(reg[0],
+ idx);
fdt_setprop(blob, off, "reg", reg,
- 3 * sizeof(u32));
-
- return 0;
+ tuple_size);
+ reg += tuple_size;
}
}
@@ -629,7 +660,7 @@ int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size)
}
}
- return -1;
+ return 0;
}
#endif
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index bd3388f..8b01c70 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -120,7 +120,13 @@
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#else
-#define CONFIG_SYS_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */
+/*
+ * No NOR-flash on Acadia when NAND-booting. We need to undef the
+ * NOR device-tree fixup code as well, since flash_info is not defined
+ * in this case.
+ */
+#define CONFIG_SYS_NO_FLASH 1
+#undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
#endif
#ifdef CONFIG_ENV_IS_IN_FLASH
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 871ef45..fd94929 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -79,7 +79,7 @@ void ft_pci_setup(void *blob, bd_t *bd);
void set_working_fdt_addr(void *addr);
int fdt_resize(void *blob);
-int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
+int fdt_fixup_nor_flash_size(void *blob);
void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
void fdt_del_node_and_alias(void *blob, const char *alias);
--
1.7.3
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