[U-Boot] [PATCH 02/14] PXA: pxa-regs.h cleanup

[Wolfgang Denk]

Dear Marek Vasut,

In message <1285226769-9619-2-git-send-email-marek.vasut at gmail.com> you wrote:
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
...
> +	debug("FDADR0 = 0x%08x\n", (unsigned int)readl(FDADR0));
> +	debug("FDADR1 = 0x%08x\n", (unsigned int)readl(FDADR1));
> +	debug("LCCR0 = 0x%08x\n", (unsigned int)readl(LCCR0));
> +	debug("LCCR1 = 0x%08x\n", (unsigned int)readl(LCCR1));
> +	debug("LCCR2 = 0x%08x\n", (unsigned int)readl(LCCR2));
> +	debug("LCCR3 = 0x%08x\n", (unsigned int)readl(LCCR3));

Is there a specific reason for the "(unsigned int)" cast? Using a
"0x%08lx" format would seem more logical to me?



> diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
> index d442fb0..4eefff2 100644
> --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
> +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
...
> +#define DCSR0		(0x40000000)  /* DMA Control / Status Register for Channel 0 */
> +#define DCSR1		(0x40000004)  /* DMA Control / Status Register for Channel 1 */
> +#define DCSR2		(0x40000008)  /* DMA Control / Status Register for Channel 2 */
> +#define DCSR3		(0x4000000c)  /* DMA Control / Status Register for Channel 3 */
> +#define DCSR4		(0x40000010)  /* DMA Control / Status Register for Channel 4 */
> +#define DCSR5		(0x40000014)  /* DMA Control / Status Register for Channel 5 */
> +#define DCSR6		(0x40000018)  /* DMA Control / Status Register for Channel 6 */
> +#define DCSR7		(0x4000001c)  /* DMA Control / Status Register for Channel 7 */
> +#define DCSR8		(0x40000020)  /* DMA Control / Status Register for Channel 8 */
> +#define DCSR9		(0x40000024)  /* DMA Control / Status Register for Channel 9 */
> +#define DCSR10		(0x40000028)  /* DMA Control / Status Register for Channel 10 */
> +#define DCSR11		(0x4000002c)  /* DMA Control / Status Register for Channel 11 */
> +#define DCSR12		(0x40000030)  /* DMA Control / Status Register for Channel 12 */
> +#define DCSR13		(0x40000034)  /* DMA Control / Status Register for Channel 13 */
> +#define DCSR14		(0x40000038)  /* DMA Control / Status Register for Channel 14 */
> +#define DCSR15		(0x4000003c)  /* DMA Control / Status Register for Channel 15 */
...

No parens needed for plain numbers. Please fix globally.

Do you plan to convert this (and the others) into a proper C struct?

...
> +///*#define SACR0		(0x40400000)  /  Global Control Register */
> +///*#define SACR1		(0x40400004)  /  Serial Audio I 2 S/MSB-Justified Control Register */
> +///*#define SASR0		(0x4040000C)  /  Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
> +///*#define SAIMR		(0x40400014)  /  Serial Audio Interrupt Mask Register */
> +///*#define SAICR		(0x40400018)  /  Serial Audio Interrupt Clear Register */
> +///*#define SADIV		(0x40400060)  /  Audio Clock Divider Register. */
> +///*#define SADR		(0x40400080)  /  Serial Audio Data Register (TX and RX FIFO access Register). */

C++ comments are not allowed.

Please remove dead code.


Best regards,

Wolfgang Denk

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