[U-Boot] [PATCH 1/4] powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
Kumar Gala
galak at kernel.crashing.org
Mon Aug 1 08:30:45 CEST 2011
From: Poonam Aggrwal <poonam.aggrwal at freescale.com>
For an IFC Erratum (A-003399) we will need to access IFC registers in
cpu_init_early_f() so expand the TLB covering CCSR to 1M.
Since we need a TLB to cover 1M we move to using TLB1 array for all the
early mappings so we can cover various sizes beyond 4k.
Additionally removed volatile from ccsr_virt declaration as its not needed
for IO accessors
Signed-off-by: Poonam Aggrwal <poonam.aggrwal at freescale.com>
Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 25 +++++++++++++++++--------
1 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 32aa94b..97e8424 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -21,15 +21,24 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * We need a dummy virtual address to access the first 4k of CCSRBAR at. This
+ * virtual address is while we are in AS=1 address space and should not conflict
+ * with CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_CCSRBAR or CONFIG_SYS_MONITOR_BASE.
+ * We use 0x1000 to make sure NULL access still cause some fault error
+ */
+#define CCSRBAR_VIRT_DUMMY (0x1000)
+
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
#ifdef CONFIG_FSL_CORENET
static void setup_ccsrbar(void)
{
u32 temp;
- volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
+ u32 *ccsr_virt = (u32 *)(CCSRBAR_VIRT_DUMMY);
volatile ccsr_local_t *ccm;
/*
@@ -60,7 +69,7 @@ static void setup_ccsrbar(void)
static void setup_ccsrbar(void)
{
u32 temp;
- volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
+ u32 *ccsr_virt = (u32 *)(CCSRBAR_VIRT_DUMMY);
temp = in_be32(ccsr_virt);
out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
@@ -85,8 +94,8 @@ void cpu_init_early_f(void)
for (i = 0; i < sizeof(gd_t); i++)
((char *)gd)[i] = 0;
- mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);
- mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
+ mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
+ mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
@@ -95,9 +104,9 @@ void cpu_init_early_f(void)
/* set up CCSR if we want it moved */
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
- mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
- /* mas1 is the same as above */
- mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G);
+ mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(12);
+ mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
+ mas2 = FSL_BOOKE_MAS2(CCSRBAR_VIRT_DUMMY, MAS2_I|MAS2_G);
mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR);
mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);
@@ -107,6 +116,6 @@ void cpu_init_early_f(void)
#endif
init_laws();
- invalidate_tlb(0);
+ invalidate_tlb(1);
init_tlbs();
}
--
1.7.3.4
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