[U-Boot] [PATCH v2] ARM926ejs: Add routines to invalidate D-Cache

[Hong Xu]

After DMA operation, we need to maintain D-Cache coherency.
We need to clean cache (write back the dirty lines) and then
make the cache invalidate as well(hence CPU will fetch data
written by DMA controller from RAM).

Tested on AT91SAM9261EK with Peripheral DMA controller.

Signed-off-by: Hong Xu <hong.xu at atmel.com>
Tested-by: Elen Song <elen.song at atmel.com>
CC: Albert Aribaud <albert.aribaud at free.fr>
CC: Heiko Schocher <hs at denx.de>
---
Changes since v1
~ Per Albert's suggestion, add invalidate_dcache_range originally defined
  in include/common.h

 arch/arm/lib/cache.c |   46 ++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 46 insertions(+), 0 deletions(-)

diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 92b61a2..0436443 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -53,3 +53,49 @@ void	__flush_dcache_all(void)
 }
 void	flush_dcache_all(void)
 	__attribute__((weak, alias("__flush_dcache_all")));
+
+void __invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	int cache_line_len;
+	unsigned long mva;
+
+#ifdef CONFIG_ARM926EJS
+
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+	cache_line_len = CONFIG_SYS_CACHELINE_SIZE;
+#else
+	cache_line_len = 32;
+#endif
+	/*
+	 * If start and stop are not aligned to cache-line,
+	 * the adjacent lines will be cleaned
+	 */
+	if ((start & (cache_line_len - 1)) != 0)
+		asm("mcr p15, 0, %0, c7, c10, 1" : : "r" (start));
+	if ((stop & (cache_line_len - 1)) != 0)
+		asm("mcr p15, 0, %0, c7, c10, 1" : : "r" (stop));
+
+	mva = start & ~(cache_line_len - 1);
+	while (mva < stop) {
+		asm("mcr p15, 0, %0, c7, c6, 1" : : "r"(mva));
+		mva += cache_line_len;
+	}
+
+	/* Drain the WB */
+	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+#endif
+
+	return;
+}
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+	__attribute__((weak, alias("__invalidate_dcache_range")));
+
+void __invalidate_dcache_all(void)
+{
+#ifdef CONFIG_ARM926EJS
+	asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+#endif
+	return;
+}
+void  invalidate_dcache_all(void)
+	__attribute__((weak, alias("__invalidate_dcache_all")));
-- 
1.7.3.3