[U-Boot] [RESEND PATCH v3 4/4] Tegra2: Use clock and pinmux functions to simplify code
Simon Glass
sjg at chromium.org
Tue Aug 16 02:42:38 CEST 2011
Signed-off-by: Simon Glass <sjg at chromium.org>
---
Changes in v2:
- Removed use of bitfield access macros
- Now uses manual shifts and masks
Changes in v3:
- Removed bitfield shift/mask macros and write these out manually
- Rebased to take account to new MMC patches
arch/arm/cpu/armv7/tegra2/ap20.c | 47 ++++++++-------------------
arch/arm/include/asm/arch-tegra2/clk_rst.h | 37 ----------------------
board/nvidia/common/board.c | 12 +++---
3 files changed, 20 insertions(+), 76 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
index e3832e2..dc5f984 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -40,23 +40,21 @@ void init_pllx(void)
u32 reg;
/* If PLLX is already enabled, just return */
- reg = readl(&pll->pll_base);
- if (reg & PLL_ENABLE)
+ if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
return;
/* Set PLLX_MISC */
- reg = CPCON; /* CPCON[11:8] = 0001 */
- writel(reg, &pll->pll_misc);
+ writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
/* Use 12MHz clock here */
- reg = (PLL_BYPASS | PLL_DIVM_VALUE);
- reg |= (1000 << 8); /* DIVN = 0x3E8 */
+ reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
+ reg |= 1000 << PLL_DIVN_SHIFT;
writel(reg, &pll->pll_base);
- reg |= PLL_ENABLE;
+ reg |= PLL_ENABLE_MASK;
writel(reg, &pll->pll_base);
- reg &= ~PLL_BYPASS;
+ reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base);
}
@@ -90,16 +88,11 @@ static void enable_cpu_clock(int enable)
* always stop the clock to CPU 1.
*/
clk = readl(&clkrst->crc_clk_cpu_cmplx);
- clk |= CPU1_CLK_STP;
-
- if (enable) {
- /* Unstop the CPU clock */
- clk &= ~CPU0_CLK_STP;
- } else {
- /* Stop the CPU clock */
- clk |= CPU0_CLK_STP;
- }
+ clk |= 1 << CPU1_CLK_STP_SHIFT;
+ /* Stop/Unstop the CPU clock */
+ clk &= ~CPU0_CLK_STP_MASK;
+ clk |= !enable << CPU0_CLK_STP_SHIFT;
writel(clk, &clkrst->crc_clk_cpu_cmplx);
clock_enable(PERIPH_ID_CPU);
@@ -177,9 +170,6 @@ static void enable_cpu_power_rail(void)
static void reset_A9_cpu(int reset)
{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 cpu;
-
/*
* NOTE: Regardless of whether the request is to hold the CPU in reset
* or take it out of reset, every processor in the CPU complex
@@ -188,19 +178,10 @@ static void reset_A9_cpu(int reset)
* are multiple processors in the CPU complex.
*/
- /* Hold CPU 1 in reset */
- cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1;
- writel(cpu, &clkrst->crc_cpu_cmplx_set);
-
- if (reset) {
- /* Now place CPU0 into reset */
- cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0;
- writel(cpu, &clkrst->crc_cpu_cmplx_set);
- } else {
- /* Take CPU0 out of reset */
- cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0;
- writel(cpu, &clkrst->crc_cpu_cmplx_clr);
- }
+ /* Hold CPU 1 in reset, and CPU 0 if asked */
+ reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
+ reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
+ reset);
/* Enable/Disable master CPU reset */
reset_set_enable(PERIPH_ID_CPU, reset);
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h
index a574c53..bd9d9ad 100644
--- a/arch/arm/include/asm/arch-tegra2/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h
@@ -140,43 +140,6 @@ struct clk_rst_ctlr {
uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
};
-#define PLL_BYPASS (1 << 31)
-#define PLL_ENABLE (1 << 30)
-#define PLL_BASE_OVRRIDE (1 << 28)
-#define PLL_DIVP_VALUE (1 << 20) /* post divider, b22:20 */
-#define PLL_DIVM_VALUE 0x0C /* input divider, b4:0 */
-
-#define SWR_UARTD_RST (1 << 1)
-#define CLK_ENB_UARTD (1 << 1)
-#define SWR_UARTA_RST (1 << 6)
-#define CLK_ENB_UARTA (1 << 6)
-
-#define SWR_CPU_RST (1 << 0)
-#define CLK_ENB_CPU (1 << 0)
-#define SWR_CSITE_RST (1 << 9)
-#define CLK_ENB_CSITE (1 << 9)
-
-#define SET_CPURESET0 (1 << 0)
-#define SET_DERESET0 (1 << 4)
-#define SET_DBGRESET0 (1 << 12)
-
-#define SET_CPURESET1 (1 << 1)
-#define SET_DERESET1 (1 << 5)
-#define SET_DBGRESET1 (1 << 13)
-
-#define CLR_CPURESET0 (1 << 0)
-#define CLR_DERESET0 (1 << 4)
-#define CLR_DBGRESET0 (1 << 12)
-
-#define CLR_CPURESET1 (1 << 1)
-#define CLR_DERESET1 (1 << 5)
-#define CLR_DBGRESET1 (1 << 13)
-
-#define CPU0_CLK_STP (1 << 8)
-#define CPU1_CLK_STP (1 << 9)
-
-#define CPCON (1 << 8)
-
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
#define CPU1_CLK_STP_SHIFT 9
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 74699de..003bd3a 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -81,20 +81,20 @@ static void clock_init_uart(void)
u32 reg;
reg = readl(&pll->pll_base);
- if (!(reg & PLL_BASE_OVRRIDE)) {
+ if (!(reg & PLL_BASE_OVRRIDE_MASK)) {
/* Override pllp setup for 216MHz operation. */
- reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP_VALUE);
- reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM_VALUE);
+ reg = PLL_BYPASS_MASK | PLL_BASE_OVRRIDE_MASK |
+ (1 << PLL_DIVP_SHIFT) | (0xc << PLL_DIVM_SHIFT);
+ reg |= (NVRM_PLLP_FIXED_FREQ_KHZ / 500) << PLL_DIVN_SHIFT;
writel(reg, &pll->pll_base);
- reg |= PLL_ENABLE;
+ reg |= PLL_ENABLE_MASK;
writel(reg, &pll->pll_base);
- reg &= ~PLL_BYPASS;
+ reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base);
}
- /* Now do the UART reset/clock enable */
#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
/* Assert UART reset and enable clock */
reset_set_enable(PERIPH_ID_UART1, 1);
--
1.7.3.1
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