[U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations

[Hong Xu]

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations
into this file.

Signed-off-by: Hong Xu <hong.xu at atmel.com>
Tested-by: Elen Song <elen.song at atmel.com>
CC: Albert Aribaud <albert.u.boot at aribaud.net>
---
Since V1
    Modified copyright line
    Fix for compiling warnings
    Changed the way to use CONFIG_SYS_CACHELINE_SIZE
    When unaligned buffer detected, emit ERROR instead of WARNING

    Do not make a common v5,v6 cache file. It seems arm946 is lack of
    Test-and-Clean DCache operation. And maybe more differents...

 arch/arm/cpu/arm926ejs/Makefile |    2 +-
 arch/arm/cpu/arm926ejs/cache.c  |  135 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 136 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/cache.c

diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index 930e0d1..5b5f330 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).o
 
 START	= start.o
-COBJS	= cpu.o
+COBJS	= cpu.o cache.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
new file mode 100644
index 0000000..756c9b1
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2011 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLUSH_CACHE_OP		0
+#define INVALIDATE_CACHE_OP	1
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+/*
+ * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+ * only b'10, aka. 32 bytes cache line len is valid
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * Flush or Invalidate DCache respectively
+ */
+static void cache_range_op(unsigned long start, unsigned long stop, int op)
+{
+	unsigned long mva;
+
+	if (op > INVALIDATE_CACHE_OP) {
+		printf("ERROR: %s - Invalid cache operation, op: %d!\n",
+			__func__, op);
+		return;
+	}
+
+	mva = start;
+	if ((mva & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
+		printf("ERROR: %s op: %d - start address 0x%08lx not aligned "
+			"to cache line size(%d bytes)\n", __func__, op, start,
+			CONFIG_SYS_CACHELINE_SIZE);
+		/* Round up starting address */
+		mva = (mva | (CONFIG_SYS_CACHELINE_SIZE - 1)) + 1;
+	}
+	if ((stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
+		printf("ERROR: %s op: %d - stop address 0x%08lx not aligned "
+			"to cache line size(%d bytes)\n", __func__, op, stop,
+			CONFIG_SYS_CACHELINE_SIZE);
+		/* Round down ending address */
+		stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	}
+
+	while (mva < stop) {
+		if (op == FLUSH_CACHE_OP)
+			asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
+		else
+			asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
+
+		mva += CONFIG_SYS_CACHELINE_SIZE;
+	}
+
+	/* Drain WB if necessary */
+	if (op == FLUSH_CACHE_OP)
+		asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+/*
+ * The buffer range to be flushed is [start, stop)
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	cache_range_op(start, stop, FLUSH_CACHE_OP);
+}
+
+void flush_dcache_all(void)
+{
+	/*
+	 * ARM926EJ-S Technical Reference Manual, Chap 2.3.8
+	 * Clean & Invalidate the entire DCache
+	 */
+	asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
+	/* Drain WB */
+	asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
+
+/*
+ * The buffer range to be invalidated is [start, stop)
+ */
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	cache_range_op(start, stop, INVALIDATE_CACHE_OP);
+}
+
+void invalidate_dcache_all(void)
+{
+	asm("mcr p15, 0, %0, c7, c6, 0\n" : : "r" (0));
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+void flush_cache(unsigned long start, unsigned long size) {}
+void flush_dcache_all(void) {}
+void flush_dcache_range(unsigned long start, unsigned long stop) {}
+void invalidate_dcache_range(unsigned long start, unsigned long stop) {}
+void invalidate_dcache_all(void) {}
+#endif
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+void invalidate_icache_all(void)
+{
+	asm("mcr p15, 0, %0, c7, c5, 0\n" : : "r" (0));
+}
+
+#else /* #ifndef CONFIG_SYS_ICACHE_OFF */
+
+void invalidate_icache_all(void) {}
+#endif
-- 
1.7.6