[U-Boot] [PATCH 2/3] powerpc/85xx: relocate CCSR before creating the initial RAM area

[Kumar Gala]

On Aug 5, 2011, at 10:36 AM, Timur Tabi wrote:

> Before main memory (DDR) is initialized, the on-chip L1 cache is used as a
> memory area for the stack and the global data (gd_t) structure.  This is
> called the initial RAM area, or initram.  The L1 cache is locked and the TLBs
> point to a non-existent address (so that there's no chance it will overlap
> main memory or any device).  The L1 cache is also configured not to write
> out to memory or the L2 cache, so everything stays in the L1 cache.
> 
> One of the things we might do while running out of initram is relocate CCSR.
> On reset, CCSR is typically located at some high 32-bit address, like
> 0xfe000000, and this may not be the best place for CCSR.  For example, on
> 36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit
> memory space.
> 
> On some future Freescale SOCs, the L1 cache will be forced to write to the
> backing store, so we can no longer have the TLBs point to non-existent address.
> Instead, we will point the TLBs to an unused area in CCSR.  In order for this
> technique to work, CCSR needs to be relocated before the initram memory is
> enabled.
> 
> Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs
> we create now for relocating CCSR are deleted after the relocation is finished.
> cpu_init_early_f() will still need to create a TLB for CCSR (at the new
> location) for normal U-Boot purposes.  This is done to keep the impact to
> existing U-Boot code minimal and to better isolate the CCSR relocation code.
> 
> Signed-off-by: Timur Tabi <timur at freescale.com>
> ---
> arch/powerpc/cpu/mpc85xx/cpu_init_early.c |   58 -------
> arch/powerpc/cpu/mpc85xx/start.S          |  234 +++++++++++++++++++++++++++++
> 2 files changed, 234 insertions(+), 58 deletions(-)

applied to 85xx next

- k