[U-Boot] [PATCH v10 4/8] nds32/ag101: cpu and init funcs of SoC ag101
Macpaul Lin
macpaul at andestech.com
Wed Aug 31 12:25:56 CEST 2011
SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.
cpu.c
According to the bootstrap procedure in n1213 Core,
to turn off watchdog timer is suggested after the
cpu is in superuser mdoe.
1. bootstrap
1.1 reset - start of Andesboot
1.2 to superuser mode - as is when reset
1.3 Turn off watchdog timer
If you take look into the start.S in n1213, you will find that
system will turn off watchdog after start.S has been retunred
from lowlevel_init.
Since the watchdog device is depends on the SoC is choosed.
It should be belonged to the SoC (ag101) folder.
watchdog.S:
If you've ran another bootloader before u-boot was started
the watchdog might have been enabled already.
lowlevel_init.S is a peripheral initial procedure of ag101.
It configures onboard dram, clock, and power settings.
It also prepars the dram environment before moving u-boot
from rom and flash into dram.
This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.
Signed-off-by: Macpaul Lin <macpaul at andestech.com>
---
Changes for v1-v4:
- Code clean up.
Changes for v5-v6:
- Split watchdog.S from lowlevel_init.S.
- Fix hardware reset by using watchdog reset in do_reset() in cpu.c.
- reset_cpu was remove inside do_reset().
- lowlevel_init.S
- Change hard code value into MARCO definitions.
- ftsmc010
- Fix FTSMC020_TPR_AT2 from 1 to 3 (0xff3ff)
- ftsdmc021
- Fix hardcoded address of CR1, CR2, TR1, TR2, BANK0 registers.
- Fix the default configuration value of FTSDMC and FTSMC controller.
- Remove some ftpmu010 and flash probe code to C functions.
Changes for v7:
- clean up.
Changes for v8-v9:
- No change.
Changes for v10:
- asm-offset.c: file added for ag101 use only.
- ag101/Makefile: add gen-asm-offset support to ag101 for lowlevel_init.S.
- Makefile: add gen-asm-offset support for NDS32 based core and SoCs.
- cpu.c: remove unused cpu_init().
- lowlevel_init.S
- Introduce SoC specific gen-asm-offset.h to lowlevel_init.S
- Replace routings by macros to made code much easier to understand.
- Add debug LED support.
- Add CONFIG_MEM_REMAP for those boards must do memort remapping.
Makefile | 3 +-
arch/nds32/cpu/n1213/ag101/Makefile | 70 ++++++++
arch/nds32/cpu/n1213/ag101/asm-offsets.c | 43 +++++
arch/nds32/cpu/n1213/ag101/cpu.c | 200 +++++++++++++++++++++++
arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 238 ++++++++++++++++++++++++++++
arch/nds32/cpu/n1213/ag101/timer.c | 204 ++++++++++++++++++++++++
arch/nds32/cpu/n1213/ag101/watchdog.S | 48 ++++++
arch/nds32/include/asm/arch-ag101/ag101.h | 68 ++++++++
8 files changed, 873 insertions(+), 1 deletions(-)
create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile
create mode 100644 arch/nds32/cpu/n1213/ag101/asm-offsets.c
create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c
create mode 100644 arch/nds32/cpu/n1213/ag101/lowlevel_init.S
create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c
create mode 100644 arch/nds32/cpu/n1213/ag101/watchdog.S
create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h
diff --git a/Makefile b/Makefile
index 03d80b7..89aebff 100644
--- a/Makefile
+++ b/Makefile
@@ -1019,7 +1019,8 @@ clean:
$(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds \
$(obj)u-boot.lds \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
- $(obj)arch/blackfin/cpu/init.{lds,elf}
+ $(obj)arch/blackfin/cpu/init.{lds,elf} \
+ $(obj)arch/nds32/cpu/$(CPU)/$(SOC)/gen-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile
new file mode 100644
index 0000000..40a0fa7
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/Makefile
@@ -0,0 +1,70 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-y := cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS := lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS += watchdog.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+$(OBJS): $(obj)gen-asm-offsets.h
+$(obj)gen-asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \
+ $(obj)gen-asm-offsets.s
+ @echo Generating $@ ; \
+ $(SRCTREE)/tools/scripts/make-asm-offsets $(obj)gen-asm-offsets.s $@
+
+$(obj)gen-asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \
+ $(src)asm-offsets.c
+ @mkdir -p $(obj)b
+ $(CC) -DDO_DEPS_ONLY \
+ $(CFLAGS) -o $@ $(src)asm-offsets.c -c -S
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
new file mode 100644
index 0000000..92ada8a
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/asm-offsets.c
@@ -0,0 +1,43 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+ OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
+ OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
+#endif
+ BLANK();
+#ifdef CONFIG_FTAHBC020S
+ OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
+ OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
+#endif
+ BLANK();
+#ifdef CONFIG_FTPMU010
+ OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0);
+#endif
+ BLANK();
+#ifdef CONFIG_FTSDMC021
+ OFFSET(FTSDMC021_TP1, ftsdmc021, tp1);
+ OFFSET(FTSDMC021_TP2, ftsdmc021, tp2);
+ OFFSET(FTSDMC021_CR1, ftsdmc021, cr1);
+ OFFSET(FTSDMC021_CR2, ftsdmc021, cr2);
+ OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr);
+ OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr);
+ OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr);
+ OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr);
+#endif
+ return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
new file mode 100644
index 0000000..0ab666e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger at sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+#ifdef CONFIG_MMU
+ unsigned long i;
+#endif
+
+ disable_interrupts();
+
+#ifdef CONFIG_MMU
+ /* turn off I/D-cache */
+ icache_disable();
+ dcache_disable();
+
+ /* flush I/D-cache */
+ invalidate_icac();
+ invalidate_dcac();
+#endif
+
+ return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ disable_interrupts();
+
+ /*
+ * reset to the base addr of andesboot.
+ * currently no ROM loader at addr 0.
+ * do not use reset_cpu(0);
+ */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+ /*
+ * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+ * automatic hardware reset when booting Linux.
+ * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+ */
+ ftwdt010_wdt_reset();
+ while (1)
+ ;
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+
+ /*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+ if (cache == ICACHE)
+ return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+ >> ICM_CFG_OFF_ISZ) - 1);
+ else
+ return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+ >> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = CACHE_LINE_SIZE(DCACHE);
+
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+ start += line_size;
+ }
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = CACHE_LINE_SIZE(ICACHE);
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+ start += line_size;
+ }
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+ dcache_flush_range(addr , addr + size);
+ icache_inval_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "ori $p0, $p0, 0x01\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+void icache_disable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "li $p1, ~0x01\n\t"
+ "and $p0, $p0, $p1\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+int icache_status(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "andi %0, $p0, 0x01\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+
+ return ret;
+}
+
+void dcache_enable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "ori $p0, $p0, 0x02\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+void dcache_disable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "li $p1, ~0x02\n\t"
+ "and $p0, $p0, $p1\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+int dcache_status(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "andi %0, $p0, 0x02\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+
+ return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
new file mode 100644
index 0000000..94308a8
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+#include "gen-asm-offsets.h"
+
+#include <asm/macro.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
+#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
+#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
+#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
+#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+
+#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
+#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
+#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
+#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
+
+#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
+
+/*
+ * parameters for the static memory controller
+ */
+#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
+#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
+
+#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
+#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
+
+/*
+ * parameters for the ahbc controller
+ */
+#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+
+#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the pmu controoler
+ */
+#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+
+/*
+ * numeric 7 segment display
+ */
+.macro led, num
+ write32 CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro wait_sdram
+ li $r0, CONFIG_FTSDMC021_BASE
+1:
+ lwi $r1, [$r0+FTSDMC021_CR2]
+ bnez $r1, 1b
+.endm
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl lowlevel_init
+lowlevel_init:
+ move $r10, $lp
+
+ led 0x0
+ jal mem_init
+
+ led 0x10
+ jal remap
+
+ led 0x20
+ ret $r10
+
+mem_init:
+ move $r11, $lp
+
+ /*
+ * mem_init:
+ * There are 2 bank connected to FTSMC020 on AG101
+ * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
+ * we need to set onboard SDRAM before remap and relocation.
+ */
+ led 0x01
+ write32 SMC_BANK0_CR_A, SMC_BANK0_CR_D ! 0x10000052
+ write32 SMC_BANK0_TPR_A, SMC_BANK0_TPR_D ! 0x00151151
+
+ /*
+ * config AHB Controller
+ */
+ led 0x02
+ write32 AHBC_BSR6_A, AHBC_BSR6_D
+
+ /*
+ * config PMU controller
+ */
+ /* ftpmu010_dlldis_disable, must do it in lowleve_init */
+ led 0x03
+ setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
+
+ /*
+ * config SDRAM controller
+ */
+ led 0x04
+ write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312
+ led 0x05
+ write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180
+ led 0x06
+ write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326
+
+ led 0x07
+ write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010
+ wait_sdram
+
+ led 0x08
+ write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004
+ wait_sdram
+
+ led 0x09
+ write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008
+ wait_sdram
+
+ led 0x0a
+ move $lp, $r11
+ ret
+
+remap:
+ move $r11, $lp
+#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
+ bal 2f
+relo_base:
+ move $r0, $lp
+#else
+relo_base:
+ mfusr $r0, $pc
+#endif /* __NDS32_N1213_43U1H__ */
+
+ /*
+ * Remapping
+ */
+ led 0x1a
+ write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001100
+
+ /* clear empty BSR registers */
+ led 0x1b
+ li $r4, CONFIG_FTSDMC021_BASE
+ li $r5, 0x0
+ swi $r5, [$r4 + FTSDMC021_BANK1_BSR]
+ swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
+ swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
+
+#ifdef CONFIG_MEM_REMAP
+ /*
+ * Copy ROM code to SDRAM base for memory remap layout.
+ * This is not the real relocation, the real relocation is the function
+ * relocate_code() is start.S which supports the systems is memory
+ * remapped or not.
+ */
+ /*
+ * Doing memory remap is essential for preparing some non-OS or RTOS
+ * applications.
+ *
+ * This is also a must on ADP-AG101 board.
+ * The reason is because the ROM/FLASH circuit on PCB board.
+ * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+ * ROM/FLASH is used to boot.
+ *
+ * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+ * and the FLASH is connected to BANK1.
+ * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+ * and the FLASH is connected to BANK0.
+ * It will occur problem when doing flash probing if the flash is at
+ * BANK0 (0x00000000) while memory remapping was skipped.
+ *
+ * Other board like ADP-AG101P may not enable this since there is only
+ * a FLASH connected to bank0.
+ */
+ led 0x11
+ li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */
+ li $r5, 0x0
+ la $r1, relo_base /* get $pc or $lp */
+ sub $r2, $r0, $r1
+ sethi $r6, hi20(_end)
+ ori $r6, $r6, lo12(_end)
+ add $r6, $r6, $r2
+1:
+ lwi.p $r7, [$r5], #4
+ swi.p $r7, [$r4], #4
+ blt $r5, $r6, 1b
+
+ /* set remap bit */
+ /*
+ * MEM remap bit is operational
+ * - use it to map writeable memory at 0x00000000, in place of flash
+ * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
+ * - after remap: flash/rom 0x80000000, sdram: 0x00000000
+ */
+ led 0x1c
+ setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
+
+#endif /* #ifdef CONFIG_MEM_REMAP */
+ move $lp, $r11
+2:
+ ret
+
+.globl show_led
+show_led:
+ li $r8, (CONFIG_DEBUG_LED)
+ swi $r7, [$r8]
+ ret
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
new file mode 100644
index 0000000..b689eab
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert at faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+ static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+ unsigned int cr;
+
+ debug("%s()\n", __func__);
+
+ /* disable timers */
+ writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ /* use 32768Hz oscillator for RTC, WDT, TIMER */
+ ftpmu010_32768osc_enable();
+#endif
+
+ /* setup timer */
+ writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+ writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+ writel(0, &tmr->timer3_match1);
+ writel(0, &tmr->timer3_match2);
+
+ /* we don't want timer to issue interrupts */
+ writel(FTTMR010_TM3_MATCH1 |
+ FTTMR010_TM3_MATCH2 |
+ FTTMR010_TM3_OVERFLOW,
+ &tmr->interrupt_mask);
+
+ cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ cr |= FTTMR010_TM3_CLOCK; /* use external clock */
+#endif
+ cr |= FTTMR010_TM3_ENABLE;
+ writel(cr, &tmr->cr);
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+ static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+ /* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+ lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+
+ debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+ debug("%s()\n", __func__);
+ reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+ static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+ /* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+ ulong now = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+
+ debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+ if (lastdec >= now) {
+ /*
+ * normal mode (non roll)
+ * move stamp fordward with absoulte diff ticks
+ */
+ timestamp += lastdec - now;
+ } else {
+ /*
+ * we have overflow of the count down timer
+ *
+ * nts = ts + ld + (TLV - now)
+ * ts=old stamp, ld=time that passed before passing through -1
+ * (TLV-now) amount of time after passing though -1
+ * nts = new "advancing time stamp"...it could also roll and
+ * cause problems.
+ */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+
+ lastdec = now;
+
+ debug("%s() returns %lx\n", __func__, timestamp);
+
+ return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+ debug("%s(%lx)\n", __func__, base);
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ debug("%s(%lx)\n", __func__, t);
+ timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+ static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+ long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+#endif
+ unsigned long now, last = readl(&tmr->timer3_counter);
+
+ debug("%s(%lu)\n", __func__, usec);
+ while (tmo > 0) {
+ now = readl(&tmr->timer3_counter);
+ if (now > last) /* count down timer overflow */
+ tmo -= TIMER_LOAD_VAL + last - now;
+ else
+ tmo -= last - now;
+ last = now;
+ }
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ debug("%s()\n", __func__);
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ return CONFIG_SYS_HZ;
+#else
+ return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S
new file mode 100644
index 0000000..fc39f3f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag101/watchdog.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag101/ag101.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+.globl turnoff_watchdog
+turnoff_watchdog:
+
+#define WD_CR 0xC
+#define WD_ENABLE 0x1
+
+ ! Turn off the watchdog, according to Faraday FTWDT010 spec
+ li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
+ lwi $p1, [$p0] ! Get the config of WD
+ andi $p1, $p1, 0x1f ! Wipe out useless bits
+ li $r0, ~WD_ENABLE
+ and $p1, $p1, $r0 ! Set WD disable
+ sw $p1, [$p0] ! Write back to WD CR
+
+ ! Disable Interrupts by clear GIE in $PSW reg
+ setgie.d
+
+ ret
+
+#endif
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..011989a
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+#define CONFIG_FTAHBC020S_BASE 0x90100000 /* AHB Controller */
+#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller (SRAM) */
+#define CONFIG_FTSDMC021_BASE 0x90300000 /* FTSDMC020/021 SDRAM Controller */
+#define CONFIG_FTDMAC020_BASE 0x90400000 /* DMA Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE 0x90500000 /* AHB-to-APB Bridge */
+#define CONFIG_FTLCDC100_BASE 0x90600000 /* LCD Controller */
+#define CONFIG_RESERVED_01_BASE 0x90700000 /* Reserved */
+#define CONFIG_RESERVED_02_BASE 0x90800000 /* Reserved */
+#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
+#define CONFIG_EXT_USB_HOST_BASE 0x90A00000 /* External USB host */
+#define CONFIG_USB_DEV_BASE 0x90B00000 /* USB Device */
+#define CONFIG_EXT_AHBPCIBRG_BASE 0x90C00000 /* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_RESERVED_03_BASE 0x90D00000 /* Reserved */
+#define CONFIG_EXT_AHBAPBBRG_BASE 0x90E00000 /* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBSLAVE01_BASE 0x90F00000 /* External AHB slave1 (LCD) */
+
+#define CONFIG_EXT_AHBSLAVE02_BASE 0x92000000 /* External AHB slave2 (FUSBH200) */
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED 0x902FFFFC /* Debug LED */
+
+/* APB Device definitions */
+#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
+#define CONFIG_FTUART010_01_BASE 0x98300000 /* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTTMR010_BASE 0x98400000 /* Counter/Timers */
+#define CONFIG_FTWDT010_BASE 0x98500000 /* Watchdog Timer */
+#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock */
+#define CONFIG_FTGPIO010_BASE 0x98700000 /* GPIO */
+#define CONFIG_FTINTC010_BASE 0x98800000 /* Interrupt Controller */
+#define CONFIG_FTIIC010_BASE 0x98A00000 /* I2C */
+#define CONFIG_RESERVED_04_BASE 0x98C00000 /* Reserved */
+#define CONFIG_FTCFC010_BASE 0x98D00000 /* Compat Flash Controller */
+#define CONFIG_FTSDC010_BASE 0x98E00000 /* SD Controller */
+
+#define CONFIG_FTSSP010_02_BASE 0x99400000 /* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTUART010_02_BASE 0x99600000 /* ST UART ? SSP 02 (UART 02 in Linux) */
+
+/* The following address was not defined in Linux */
+#define CONFIG_FTUART010_03_BASE 0x98200000 /* FF UART 3 */
+#define CONFIG_FTSSP010_01_BASE 0x98B00000 /* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_IRDA_BASE 0x98900000 /* IrDA */
+#define CONFIG_PMW_BASE 0x99100000 /* PWM - Pulse Width Modulator Controller */
+
+#endif /* __AG101_H */
--
1.7.3.5
More information about the U-Boot
mailing list