[U-Boot] [PATCH 6/6] p1021mds: add QE and UEC support

[Scott Wood]

On Mon, 31 Jan 2011 22:14:45 -0500
Haiying Wang <Haiying.Wang at freescale.com> wrote:

> On Mon, 2011-01-31 at 15:28 -0600, Kumar Gala wrote:
> > On Jan 31, 2011, at 2:50 PM, Haiying Wang wrote:
> > 
> > > On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote:
> > >>> 
> > >>> +#ifdef CONFIG_P1021
> > >>> +	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> > >>> +
> > >>> +	/* QE9 and QE12 need to be set for enabling QE MII managment signals */
> > >>> +	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
> > >>> +	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
> > >>> +#endif
> > >> ...
> > >> 
> > >> Can we please avoid having board specific code in common files?
> > > I wish I could, but only P1021 has such pin mux problems.
> > > 
> > >> If this is really necessary, it shoud be a feature-specific #define,
> > >> not a board specific one.
> > > I don't know whether this *feature* will show up on other SoC. But if
> > > you insist, I can use CONFIG_QE_PIN_MUX.
> > > 
> > > Thanks.
> > > 
> > > Haiying
> > 
> > I think pin muxing is a board level decision so it seems like board code is the right place for it.
> > 
> If it is a one time setting, there should be no problem to put it into
> board code. But these pin settings need to be done before any usage of
> phy read/write (accessing MDIO/MDC), and need to be released after the
> usage of phy, thus the devices connected to eLBC like NAND flash/BCSR
> can be accessed. If we use board code to set/release the pin, we don't
> know when the phy access and nand flash access will happen.

Is this actually a board issue or an SoC issue?

-Scott