[U-Boot] [PATCH] mpc83xx: Use correct register to calculate clocks.

[Joakim Tjernlund]

Ping?

Kim are you maintaining 83xx or should I poke someone else?

 Jocke

>
> Use SPMR instead of HRCWL when calculating clocks as HCRWL
> may be changed and the CPU will not pick up all changes
> until there is a POR. u-boot will think SPMF has changed and get
> the clocks wrong.
>
> Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund at transmode.se>
> ---
>  arch/powerpc/cpu/mpc83xx/speed.c |   15 ++++++++-------
>  include/mpc83xx.h                |    7 +++++++
>  2 files changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
> index 500eef1..55290b4 100644
> --- a/arch/powerpc/cpu/mpc83xx/speed.c
> +++ b/arch/powerpc/cpu/mpc83xx/speed.c
> @@ -159,7 +159,7 @@ int get_clocks(void)
>  #endif
>     }
>
> -   spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
> +   spmf = ((im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT);
>     csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
>
>     sccr = im->clk.sccr;
> @@ -387,7 +387,7 @@ int get_clocks(void)
>  #endif
>
>     lbiu_clk = csb_clk *
> -              (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
> +              (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
>     lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
>     switch (lcrr) {
>     case 2:
> @@ -401,11 +401,12 @@ int get_clocks(void)
>     }
>
>     mem_clk = csb_clk *
> -        (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
> -   corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
> +        (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
> +   corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
> +
>  #if defined(CONFIG_MPC8360)
>     mem_sec_clk = csb_clk * (1 +
> -             ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
> +             ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
>  #endif
>
>     corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
> @@ -437,8 +438,8 @@ int get_clocks(void)
>     }
>
>  #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
> -   qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
> -   qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
> +   qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
> +   qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
>     qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
>     brg_clk = qe_clk / 2;
>  #endif
> diff --git a/include/mpc83xx.h b/include/mpc83xx.h
> index 5214911..a46a3aa 100644
> --- a/include/mpc83xx.h
> +++ b/include/mpc83xx.h
> @@ -642,14 +642,21 @@
>  /* SPMR - System PLL Mode Register
>   */
>  #define SPMR_LBIUCM         0x80000000
> +#define SPMR_LBIUCM_SHIFT      31
>  #define SPMR_DDRCM         0x40000000
> +#define SPMR_DDRCM_SHIFT      30
>  #define SPMR_SPMF         0x0F000000
> +#define SPMR_SPMF_SHIFT      24
>  #define SPMR_CKID         0x00800000
>  #define SPMR_CKID_SHIFT         23
>  #define SPMR_COREPLL         0x007F0000
> +#define SPMR_COREPLL_SHIFT      16
>  #define SPMR_CEVCOD         0x000000C0
> +#define SPMR_CEVCOD_SHIFT      6
>  #define SPMR_CEPDF         0x00000020
> +#define SPMR_CEPDF_SHIFT      5
>  #define SPMR_CEPMF         0x0000001F
> +#define SPMR_CEPMF_SHIFT      0
>
>  /* OCCR - Output Clock Control Register
>   */
> --
> 1.7.3.4
>
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