[U-Boot] [PATCH 2/4 v2] powerpc/85xx: Add more P1021 defines

[Haiying.Wang at freescale.com]

From: Haiying Wang <Haiying.Wang at freescale.com>

Signed-off-by: Haiying Wang <Haiying.Wang at freescale.com>
---
v2: re-number the res defines in immap_85xx.h, make changes to P1021 specific
defines based on the latest commit in u-boot-85xx git tree.
 arch/powerpc/include/asm/config_mpc85xx.h |    4 ++++
 arch/powerpc/include/asm/immap_85xx.h     |   24 +++++++++++++++---------
 2 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d7d1fb6..b25cd30 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -125,6 +125,10 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
+
 
 #elif defined(CONFIG_P1022)
 #define CONFIG_MAX_CPUS			2
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 6bd83ba..99ecb83 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1942,29 +1942,35 @@ typedef struct ccsr_gur {
 	u8	res9[12];
 	u32	pvr;		/* Processor version */
 	u32	svr;		/* System version */
-	u8	res10a[8];
+	u8	res10[8];
 	u32	rstcr;		/* Reset control */
 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
-	u8	res10b[76];
+	u8	res11a[76];
 	par_io_t qe_par_io[7];
-	u8	res10c[1600];
+	u8	res11b[1600];
+#elif defined(CONFIG_P1021)
+	u8      res11a[12];
+	u32     iovselsr;
+	u8      res11b[60];
+	par_io_t qe_par_io[3];
+	u8      res11c[1496];
 #else
-	u8	res10b[1868];
+	u8	res11a[1868];
 #endif
 	u32	clkdvdr;	/* Clock Divide register */
-	u8	res10d[1532];
+	u8	res12[1532];
 	u32	clkocr;		/* Clock out select */
-	u8	res11[12];
+	u8	res13[12];
 	u32	ddrdllcr;	/* DDR DLL control */
-	u8	res12[12];
+	u8	res14[12];
 	u32	lbcdllcr;	/* LBC DLL control */
-	u8	res13[248];
+	u8	res15[248];
 	u32	lbiuiplldcr0;	/* LBIU PLL Debug Reg 0 */
 	u32	lbiuiplldcr1;	/* LBIU PLL Debug Reg 1 */
 	u32	ddrioovcr;	/* DDR IO Override Control */
 	u32	tsec12ioovcr;	/* eTSEC 1/2 IO override control */
 	u32	tsec34ioovcr;	/* eTSEC 3/4 IO override control */
-	u8	res15[61648];
+	u8	res16[61648];
 } ccsr_gur_t;
 #endif
 
-- 
1.7.3.1.50.g1e633