[U-Boot] P2020 SPL L2 clearing

[Kumar Gala]

On Feb 9, 2011, at 2:06 AM, Fabian Cenedese wrote:

> 
>>>> I'm creating a SPL u-boot image for our board. In the file
>>>> arch/powerpc/cpu/mpc85xx/cpu_init_nand.c is the setup for
>>>> the L2 cache as SRAM. In the end is a loop that fills the
>>>> cache with 0 (512KB in this case).
>>>> 
>>>> 1. Why is the access byte-wise and not dword-wise? This
>>>> is only for mpc85xx and I think they all can access the cache
>>>> with 32bits instead of just 8. That would speed up by factor 4
>>>> (confirmed in my tests with P2020).
>> 
>> No real reason, probably historic and no one noticed.  Patch welcome to change this to 32-bit accesses, not really sure why we just dont call memset.
> 
> I can try that too and see how it goes. I will test this for my board
> and send a patch once I get my way around git (didn't use it so far).
> 
>>>> 2. Why does the cache to be cleared at all? L2-SRAM is usually
>>>> just used to copy in the second part of the u-boot image, so
>>>> the 0s will be overwritten again anyway.
>> 
>> This needs to be done because we enable ECC.
> 
> Isn't this an optional feature? Shouldn't this loop be enclosed in
> # ifdef CONFIG_DDR_ECC or doesn't this apply to L2-SRAM?

No, its not optional for the L2 cache (especially when we are in SRAM mode).  Its also independent of DDR ECC.

- k