[U-Boot] Altering cpu/mpc85xx/start.S to set GPIO

[Aggrwal Poonam-B10812]

> -----Original Message-----
> From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de]
> On Behalf Of Kumar Gala
> Sent: Thursday, February 10, 2011 1:54 PM
> To: Rick Ramstetter
> Cc: u-boot at lists.denx.de; Thomas Taranowski
> Subject: Re: [U-Boot] Altering cpu/mpc85xx/start.S to set GPIO
> 
> 
> On Feb 10, 2011, at 1:20 AM, Rick Ramstetter wrote:
> 
> > I am testing on an e500 core P2020 QorIQ (mpc85xx). As part of this
> > testing, I would like to set a GPIO pin high (aka "turn on an led")
> > during extremely early U-boot code.
> >
> > I have modified cpu/mpc85xx/start.S to (1) set GPIMR for one gpio pin,
> > (2) set GPDIR for the same gpio pin, and (3) set GPDAT for the same
> gpio pin.
> > The writes I have introduced(to GPDAT etc) occur directly after the
> > PPC exception vectors are set. The relevant portion of my modified
> > start.S is attached below.
> >
> > The problem I'm having is that the first "stw" instruction
> > (specifically, "stw 1,0(9)") sends the core into the e00 exception
> > vector. This exception is set in start.S as STD_EXCEPTION(0x0e00,
> > InstructionTLBError, UnknownException). After the exception occurs,
> > the processor halts at 0xfff80e00.
> >
> > As per the P2020 QoriQ manual's section 4.5.3 (p. 4-48, "QorIQ P2020
> > Integrated Processor Reference Manual"), I ought to be able to access
> > CCSRBAR without mapping it through a TLB; the board in question is
> > configured to boot from eSPI. As the memory mapped gpio pins are in
> > ccsr space, I am left quite confused as to why such accesses are
> > causing a TLB exception.
TLB is required to access CCSRBAR space.
> >
> > Can anyone offer any pointers on what I'm doing wrong?
> >
> > Thank you,
> > -Rick
> >
> > Modified start.s follows:
> > -------------------------------------------------------
> >
> > start_e500:
> >        /* L1 */
> > li r0,2
> > mtspr L1CSR0,r0 /* invalidate d-cache */ mtspr L1CSR1,r0 /* invalidate
> > i-cache */ mfspr r1,DBSR mtspr DBSR,r1 /* Clear all valid bits */
> >
> > /* Enable L1 Caches early  */
> > lis r2,L1CSR0_CPE at H /* enable parity */ ori r2,r2,L1CSR0_DCE mtspr
> > L1CSR0,r2 /* enable L1 Dcache */ isync mtspr L1CSR1,r2 /* enable L1
> > Icache */ isync msync
> >    /* Setup interrupt vectors */
> > lis r1,TEXT_BASE at h
> > mtspr IVPR,r1
> >
> > li r1,0x0100
> > mtspr IVOR0,r1 /* 0: Critical input */ li r1,0x0200 mtspr IVOR1,r1 /*
> > 1: Machine check */ li r1,0x0300 mtspr IVOR2,r1 /* 2: Data storage */
> > li r1,0x0400 mtspr IVOR3,r1 /* 3: Instruction storage */ li r1,0x0500
> > mtspr IVOR4,r1 /* 4: External interrupt */ li r1,0x0600 mtspr IVOR5,r1
> > /* 5: Alignment */ li r1,0x0700 mtspr IVOR6,r1 /* 6: Program check */
> > li r1,0x0800 mtspr IVOR7,r1 /* 7: floating point unavailable */ li
> > r1,0x0900 mtspr IVOR8,r1 /* 8: System call */
> > /* 9: Auxiliary processor unavailable(unsupported) */ li r1,0x0a00
> > mtspr IVOR10,r1 /* 10: Decrementer */ li r1,0x0b00 mtspr IVOR11,r1 /*
> > 11: Interval timer */ li r1,0x0c00 mtspr IVOR12,r1 /* 12: Watchdog
> > timer */ li r1,0x0d00 mtspr IVOR13,r1 /* 13: Data TLB error */ li
> > r1,0x0e00 mtspr IVOR14,r1 /* 14: Instruction TLB error */ li r1,0x0f00
> > mtspr IVOR15,r1 /* 15: Debug */
> >
> > /* Clear and set up some registers. */
> > li      r0,0x0000
> > lis r1,0xffff
> > mtspr DEC,r0 /* prevent dec exceptions */ mttbl r0 /* prevent fit &
> > wdt exceptions */ mttbu r0 mtspr TSR,r1 /* clear all timer exception
> > status */ mtspr TCR,r0 /* disable all */ mtspr ESR,r0 /* clear
> > exception syndrome register */ mtspr MCSR,r0 /* machine check syndrome
> > register */ mtxer r0 /* clear integer exception register */
> >
> >
> >     /* BEGIN MODIFICATIONS */
> >     /* TURN ON THE LED */
> >     s 9,0xff70
> 
> is this a typo?
> 
> >     lis 11,0xff70
> >     lis 10,0xff70
> >     lis 1,0x1
> >
> >     /* set low 16 bits of r9,r10,r11 */
> >     ori 9,9,64512          /* 0xfc00 */
> >     ori 10,10,64520        /* 0xfc08 */
> >     ori 11,11,64528        /* 0xfc10 */
> >
> >     /* push contents of r1 to r9,r10,r11 */
> >     stw 1,0(9)
> >     stw 1,0(11)
> >     stw 1,0(10)
> >
> >    /* for purposes of this message, you can assume the following loop
> > exists (or not) */
> >      b .
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