[U-Boot] P2020 SPL L2 clearing

[Kumar Gala]

On Feb 11, 2011, at 8:34 AM, Fabian Cenedese wrote:

> 
>>>> 2. Why does the cache to be cleared at all? L2-SRAM is usually
>>>> just used to copy in the second part of the u-boot image, so
>>>> the 0s will be overwritten again anyway.
>> 
>> This needs to be done because we enable ECC.
> 
> I'm still trying to get my head around this. From looking at the code
> this doesn't seem to be necessary. The ECC errors are disabled
> before L2 is configured as SRAM:
> 
> cpu_init_f (NAND)
>        /* set MBECCDIS=1, SBECCDIS=1 */
>        out_be32(&l2cache->l2errdis,
>                (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
> 
>        /* set L2E=1 & L2SRAM=001 */
>        out_be32(&l2cache->l2ctl,
>                (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
> 
> And these ECC disable bits are only cleared once the u-boot has
> already been copied to RAM and L2 is really used as cache:
> 
> cpu_init_r
>                /* set MBECCDIS=0, SBECCDIS=0 */
>                clrbits_be32(&l2cache->l2errdis,
>                                (MPC85xx_L2ERRDIS_MBECC |
>                                 MPC85xx_L2ERRDIS_SBECC));
> 
> So am I getting something wrong?

Nope, I was reading that is enabling ECC, wasn't paying attention that its ERROR disable

So the clearing out isn't necessary.

- k