[U-Boot] [i.MX51 interrupt]

[arden jay]

Hi,

I’m now trying interrupt in uboot, the code to initial tzic is
referred from tzic.c in kernel. (see mxc_tzic_init_irq below)
After that, I turn on INT 0~63 by:
writel(0xffffffff, TZIC_ENSET0);
writel(0xffffffff, TZIC_ENSET0 + 4);

But I always cannot see any status change reflected in TZIC_HIPND
(High Priority pending register).

The following is the output:
BBG U-Boot > off
MXC IRQ initialized, controller type: 0x403
INT enable, 0xffffffff
INT enable, 0xffffffff
INT enable, 0x0
INT enable, 0x0
BBG U-Boot > intr
pend INT, 0x0
pend INT, 0x0
pend INT, 0x0
pend INT, 0x0

Question:
1.	from entry-macro.S, it also uses High Priority pending register for
it, or I am wrong?
2.	Anything I miss for this?


void mxc_tzic_init_irq(void)
{
                int i;
                u32 v;

                /* put the TZIC into the reset value with
                * all interrupts disabled
                */
                i = readl(TZIC_INTCNTL);
                writel(0x80010001, TZIC_INTCNTL);
                i = readl(TZIC_INTCNTL);

                writel(0x1f, TZIC_PRIOMASK);
                i = readl(TZIC_PRIOMASK);

                writel(0x02, TZIC_SYNCCTRL);
                i = readl(TZIC_SYNCCTRL);

                /* set all to non-secure */
                for (i = 0; i < 4; i++) {
                                writel(0xFFFFFFFF, TZIC_INTSEC0 + i * 4);
                }

                /* disable all interrupts */
                for (i = 0; i < 4; i++) {
                                writel(0, TZIC_ENCLEAR0 + i * 4);
                                //writel(0xffffffff, TZIC_PRIORITY0 + i * 4);
                }

                v = readl(TZIC_INTTYPE);
                printf("MXC IRQ initialized, controller type: 0x%x\n", v);
#if 1
                for (i = 0; i < 4; i++) {
                                v = readl(TZIC_ENSET0 + i * 4);
                                printf("after clear, INT enable, 0x%x\n", v);
                }
#endif
}

-- 
cheers,
jay