[U-Boot] [PATCH] fsl_esdhc: Correcting esdhc timeout counter calculation

[Wolfgang Denk]

Dear Fleming Andy-AFLEMING,

In message <D4848E4B-3C47-4D5C-A171-A69439660C42 at freescale.com> you wrote:
> 
> > Does this not depend on the units used for speed, and thus in the end
> > on CONFIC_SYS_HZ ?
> 
> No, but that wasn't apparent because I didn't mention the units of
> 2^(13+timeout). It is in units of sd clocks.
> 
> So: num sd clocks = (sd clocks per sec) * 0.25 sec =
> mmc->tran_speed/4 = 2^(13+regval).
> 
> Now, it is true that the actual speed of the sd clock is going to
> depend on CONFIG_SYS_HZ, in that a tran_speed of 25MHz may not be
> perfectly achievable with available dividers, but this code is not
> taking that into account, and the fact that it's rounding up to the
> next power of two should take care of that.

Fine.  Can we please add such explanation to the code?

Thanks.

Best regards,

Wolfgang Denk

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