[U-Boot] [PATCH] fsl_pci: Update PCIe boot ouput

[Kumar Gala]

On Dec 28, 2010, at 5:47 PM, Peter Tyser wrote:

> This change does the following:
> - Adds printing of negotiated link width.  This information can be
>  useful when debugging PCIe issues.
> - Makes it optional for boards to implement board_serdes_name().
>  Previously boards that did not implement it would print unsightly
>  output such as "PCIE1: Connected to <NULL>..."
> - Rewords the PCIe boot output to reduce line length and to make it
>  clear that the "base address XYZ" value refers to the base address of
>  the internal processor PCIe registers and not a standard PCI BAR
>  value.
> - Changes "PCIE" output to the standard "PCIe"
> 
> Before change:
> PCIE1: connected to <NULL> as Root Complex (base addr ef008000)
>  01:00.0     - 10b5:8518 - Bridge device
>   02:01.0    - 10b5:8518 - Bridge device
>   02:02.0    - 10b5:8518 - Bridge device
>   02:03.0    - 10b5:8518 - Bridge device
> PCIE1: Bus 00 - 05
> PCIE2: connected to <NULL> as Endpoint (base addr ef009000)
> PCIE2: Bus 06 - 06
> 
> After change:
> PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000
>  01:00.0     - 10b5:8518 - Bridge device
>   02:01.0    - 10b5:8518 - Bridge device
>   02:02.0    - 10b5:8518 - Bridge device
>   02:03.0    - 10b5:8518 - Bridge device
> PCIe1: Bus 00 - 05
> PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000
> PCIe2: Bus 06 - 06
> 
> Signed-off-by: Peter Tyser <ptyser at xes-inc.com>
> ---
> This applies to Kumar's u-boot-85xx.git 'dev' branch.

applied to 85xx

- k