[U-Boot] [PATCH 3/3] fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)

[Kumar Gala]

From: Roy Zang <tie-fei.zang at freescale.com>

False multi-bit ECC errors will be reported by the eSDHC buffer which
can trigger a reset request.

We disable all ECC error checking on SDHC.

Signed-off-by: Roy Zang <tie-fei.zang at freescale.com>
Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c |    3 +++
 arch/powerpc/cpu/mpc85xx/cpu_init.c   |   10 +++++++++-
 include/configs/P4080DS.h             |    1 +
 3 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index d5c34c8..4e2cb4a 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -56,6 +56,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
 	puts("Work-around for Erratum ESDHC135 enabled\n");
 #endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
+	puts("Work-around for Erratum ESDHC136 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 4a6cc65..c14b622 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Modified by Xianghua Xiao, X.Xiao at motorola.com
@@ -388,6 +388,14 @@ int cpu_init_r(void)
 	setup_mp();
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
+	{
+		void *p;
+		p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+		setbits_be32(p, 1 << (31 - 14));
+	}
+#endif
+
 #ifdef CONFIG_SYS_LBC_LCRR
 	/*
 	 * Modify the CLKDIV field of LCRR register to improve the writing
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index a15dd76..4dd7faa 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -37,6 +37,7 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
 
 #define CONFIG_SYS_P4080_ERRATUM_CPU22
 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
-- 
1.6.0.6