[U-Boot] [PATCH 6/8] armv7: adapt omap4 to the new cache maintenance framework

[Aneesh V]

Dear Wolfgang,

On Monday 10 January 2011 04:22 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1293018898-13253-7-git-send-email-aneesh at ti.com>  you wrote:
>> adapt omap4 to the new layered cache maintenance framework
>>
>> Signed-off-by: Aneesh V<aneesh at ti.com>
>
>> +/*
>> + * Outer cache related functions
>> + */
>> +#ifndef CONFIG_SYS_NO_DCACHE
>
> Do we really need such a #define?  Where is CONFIG_SYS_NO_DCACHE
> documented?

I shall add documentation if it doesn't exist. But I see that it's
already being used.
IMO, it's good to have this option:
1. Not all boards may like to enable data cache.
2. Disabling caches may be one thing you might want to try while
debugging issues.
3. CPUs that do not have cache operations and initialization defined
yet might want to keep it disabled.

>
>> +void v7_setup_outer_cache_ops(void)
>> +{
>> +#ifndef CONFIG_L2_OFF
>
> Should this be CONFIG_L2_OFF or CONFIG_SYS_L2_OFF?  Where is
> CONFIG_SYS_L2_OFF documented?

CONFIG_L2_OFF is also aready being used. That's why I used it.

A handful of board config files are using it, but in actual code it's
only referenced by armv7 code.

Shall I change them all to CONFIG_SYS_L2_OFF
I shall add documentation.

>
>
>> @@ -45,3 +47,18 @@ lowlevel_init:
>>   	 */
>>   	bl	s_init
>>   	pop	{ip, pc}
>> +
>> +set_pl310_ctrl_reg:
>> +        PUSH	{r4-r11, lr}	@ save registers - ROM code may pollute
>> +				@ our registers
>> +        LDR	r12, =0x102	@ Set PL310 control register - value in R0
>> +        SMC	#0		@ call ROM Code API to set control register
>> +        POP	{r4-r11, pc}
>
> Indentation by TAB, please.

Sure. I will take care in future. BTW, that was not caught by
checkpatch.pl. Is there anyway to catch such errors using some tool?

>
>
> Best regards,
>
> Wolfgang Denk
>

Best regards,
Aneesh