[U-Boot] [PATCH] ppc4xx: Support multiple FPGAs
Stefan Roese
sr at denx.de
Wed Jan 12 15:16:50 CET 2011
Hi Dirk,
On Monday 10 January 2011 13:33:24 Dirk Eibach wrote:
> Add support for multiple FPGAs per board for gdsys
> 405ep architecture.
>
> Signed-off-by: Dirk Eibach <eibach at gdsys.de>
> ---
> arch/powerpc/include/asm/global_data.h | 2 +-
> board/gdsys/405ep/405ep.c | 62 +++++----
> board/gdsys/405ep/dlvision-10g.c | 214
> ++++++++++++++++++++++++------- board/gdsys/405ep/io.c |
> 8 +-
> board/gdsys/405ep/iocon.c | 14 +-
> board/gdsys/common/Makefile | 1 +
> board/gdsys/common/fpga.h | 12 +-
> include/configs/dlvision-10g.h | 33 ++++-
> include/configs/io.h | 7 +-
> include/configs/iocon.h | 27 ++++-
> 10 files changed, 275 insertions(+), 105 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/global_data.h
> b/arch/powerpc/include/asm/global_data.h index 4068e85..fb7da21 100644
> --- a/arch/powerpc/include/asm/global_data.h
> +++ b/arch/powerpc/include/asm/global_data.h
> @@ -173,7 +173,7 @@ typedef struct global_data {
> unsigned long kbd_status;
> #endif
> #ifdef CONFIG_405EP
> - unsigned fpga_state;
> + unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
> #endif
Hmmm. Again, not 405_EP specific. And can't you squash this change with the
change from the dlvision-10g board?
> #if defined(CONFIG_WD_MAX_RATE)
> unsigned long long wdt_last; /* trace watch-dog triggering rate */
> diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
> index c2d9455..84ea573 100644
> --- a/board/gdsys/405ep/405ep.c
> +++ b/board/gdsys/405ep/405ep.c
> @@ -39,24 +39,26 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -int get_fpga_state(void)
> +int get_fpga_state(unsigned dev)
> {
> - return gd->fpga_state;
> + return gd->fpga_state[dev];
> }
>
> -void print_fpga_state(void)
> +void print_fpga_state(unsigned dev)
> {
> - if (gd->fpga_state & FPGA_STATE_DONE_FAILED)
> + if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
> puts(" Waiting for FPGA-DONE timed out.\n");
> - if (gd->fpga_state & FPGA_STATE_REFLECTION_FAILED)
> + if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
> puts(" FPGA reflection test failed.\n");
> }
>
> int board_early_init_f(void)
> {
> + unsigned k;
> unsigned ctr;
>
> - gd->fpga_state = 0;
> + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
> + gd->fpga_state[k] = 0;
>
> mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
> mtdcr(UIC0ER, 0x00000000); /* disable all ints */
> @@ -87,13 +89,15 @@ int board_early_init_f(void)
> /*
> * wait for fpga-done
> */
> -#warning this will not work for dlvision-10g
> - ctr = 0;
> - while (!(in_le16((void *)LATCH2_BASE) & 0x0010)) {
> - udelay(100000);
> - if (ctr++ > 5) {
> - gd->fpga_state |= FPGA_STATE_DONE_FAILED;
> - break;
> + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
> + ctr = 0;
> + while (!(in_le16((void *)LATCH2_BASE)
> + & CONFIG_SYS_FPGA_DONE(k))) {
> + udelay(100000);
> + if (ctr++ > 5) {
> + gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
> + break;
> + }
> }
> }
>
> @@ -104,20 +108,24 @@ int board_early_init_f(void)
> out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
> out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
>
> - /*
> - * wait for fpga out of reset
> - * fail ungraceful if fpga is not working properly
> - */
> - ctr = 0;
> - while (1) {
> - fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
> - if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
> - REFLECTION_TESTPATTERN_INV)
> - break;
> - udelay(100000);
> - if (ctr++ > 5) {
> - gd->fpga_state |= FPGA_STATE_REFLECTION_FAILED;
> - break;
> + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
> + /*
> + * wait for fpga out of reset
> + * fail ungraceful if fpga is not working properly
> + */
> + ctr = 0;
> + while (1) {
> + fpga_set_reg(k, CONFIG_SYS_FPGA_RFL_LOW,
> + REFLECTION_TESTPATTERN);
> + if (fpga_get_reg(k, CONFIG_SYS_FPGA_RFL_HIGH) ==
> + REFLECTION_TESTPATTERN_INV)
> + break;
> + udelay(100000);
> + if (ctr++ > 5) {
> + gd->fpga_state[k] |=
> + FPGA_STATE_REFLECTION_FAILED;
> + break;
> + }
> }
> }
>
> diff --git a/board/gdsys/405ep/dlvision-10g.c
> b/board/gdsys/405ep/dlvision-10g.c index e704f74..c217dfe 100644
> --- a/board/gdsys/405ep/dlvision-10g.c
> +++ b/board/gdsys/405ep/dlvision-10g.c
> @@ -28,63 +28,98 @@
> #include <asm/ppc4xx-gpio.h>
>
> #include "../common/fpga.h"
> +#include "../common/osd.h"
>
> enum {
> REG_VERSIONS = 0x0002,
> - REG_FPGA_FEATURES = 0x0004,
> - REG_FPGA_VERSION = 0x0006,
> + REG_FPGA_VERSION = 0x0004,
> + REG_FPGA_FEATURES = 0x0006,
> };
>
> enum {
> - UNITTYPE_CCD_SWITCH = 1,
> + UNITTYPE_VIDEO_USER = 0,
> + UNITTYPE_MAIN_USER = 1,
> + UNITTYPE_VIDEO_SERVER = 2,
> + UNITTYPE_MAIN_SERVER = 3,
> };
>
> enum {
> - HWVER_100 = 0,
> + HWVER_101 = 0,
> HWVER_110 = 1,
> - HWVER_121 = 2,
> - HWVER_122 = 3,
> };
>
> -/*
> - * Check Board Identity:
> - */
> -int checkboard(void)
> +enum {
> + AUDIO_NONE = 0,
> + AUDIO_TX = 1,
> + AUDIO_RX = 2,
> + AUDIO_RXTX = 3,
> +};
> +
> +enum {
> + SYSCLK_156250 = 2,
> +};
> +
> +enum {
> + RAM_NONE = 0,
> + RAM_DDR2_32 = 1,
> + RAM_DDR2_64 = 2,
> +};
> +
> +static void print_fpga_info(unsigned dev)
> {
> - char *s = getenv("serial#");
> - u16 versions = fpga_get_reg(REG_VERSIONS);
> - u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
> - u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
> + u16 versions = fpga_get_reg(dev, REG_VERSIONS);
> + u16 fpga_version = fpga_get_reg(dev, REG_FPGA_VERSION);
> + u16 fpga_features = fpga_get_reg(dev, REG_FPGA_FEATURES);
> unsigned unit_type;
> unsigned hardware_version;
> - unsigned feature_channels;
> - unsigned feature_expansion;
> - int fpga_state = get_fpga_state();
> + unsigned feature_compression;
> + unsigned feature_rs232;
> + unsigned feature_audio;
> + unsigned feature_sysclock;
> + unsigned feature_ramconfig;
> + unsigned feature_carrier_speed;
> + unsigned feature_carriers;
> + unsigned feature_video_channels;
> + int fpga_state = get_fpga_state(dev);
> +
> + printf("FPGA%d: ", dev);
>
> - unit_type = (versions & 0xf000) >> 12;
> hardware_version = versions & 0x000f;
> - feature_channels = fpga_features & 0x007f;
> - feature_expansion = fpga_features & (1<<15);
> -
> - printf("Board: ");
> -
> - printf("DLVision 10G");
>
> - if (s != NULL) {
> - puts(", serial# ");
> - puts(s);
> + if (fpga_state
> + && !((hardware_version == HWVER_101)
> + && (fpga_state == FPGA_STATE_DONE_FAILED))) {
> + puts("not available\n");
> + print_fpga_state(dev);
> + return;
> }
>
> - if (fpga_state) {
> - puts("\nFPGA: not available\n");
> - print_fpga_state();
> - return 0;
> - } else
> - puts("\n ");
> -#if 0
> + unit_type = (versions >> 4) & 0x000f;
> + hardware_version = versions & 0x000f;
So now you enable this "dead" code. And you are changing many lines that you
introduced with the patch before. Perhaps it makes more sense to squash this
patch with the dlvision-10g patch. What do you think?
Cheers,
Stefan
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de
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