[U-Boot] [PATCH 4/4] powerpc: Add LINK_OFF calls in early C-code.

[Scott Wood]

On Tue, 18 Jan 2011 21:39:23 +0100
Joakim Tjernlund <joakim.tjernlund at transmode.se> wrote:

> Scott Wood <scottwood at freescale.com> wrote on 2011/01/18 21:24:16:
> > I don't see why MPC8xx's MMU couldn't be used for this, although it
> > might be a tight fit if you want to get everything into the pinned TLB
> > entries.
> 
> I think it is harder that that. You probably need a tlb miss handler.

Well, as I said, it might be a tight fit.  If you can't fit everything
within the pinned entries, then you'll need a TLB miss handler, but it
could be a simple handler that will insert a non-cacheable
identity-mapped entry for whatever address faulted (cacheable regions
are covered by pinned entries and won't fault in the first place).  Or
possibly have an above/below address threshold for determining
cacheability.

After relocation, you can turn off the MMU, so it's only things you
access before relocation that need to fit in the TLB.

> > Should we be talking about all boards, if the only user of this so far
> > is on hardware that can do it in a less-intrusive way?
> >
> > Another thing to keep in mind is that Joakim's approach also won't work
> > on all boards -- you need hardware that is capable of selecting from
> > different entry points, where the entry address itself changes rather
> > than flash banks being flipped around.
> 
> No, you only need gcc support for msingle-pic-base and some extra RAM
> to hold the GOT(about 8KB would do I think) while still in flash.
> Ah, you mean how to select which image to select? That is a small
> piece of SW that checks both images and chooses the valid one and jumps
> there.

OK, I thought you were using something like a DIP switch to toggle
low/high exception vectors, and getting different entry points that way.

-Scott