[U-Boot] [PATCH] sh: add support for sh7757lcr board

[Nobuhiro Iwamatsu]

Hi,

2011/1/19 Wolfgang Denk <wd at denx.de>:
> Dear Yoshihiro Shimoda,
>
> In message <4D33C15C.9030801 at renesas.com> you wrote:
>> The R0P7757LC0030RL board has SH7757, 256MB DDR3-SDRAM, SPI ROM,
>> Ethernet, and more.
>>
>> This patch supports the following functions:
>>  - 256MB DDR3-SDRAM
>>  - SPI ROM
>>  - Ethernet
>>
>> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh at renesas.com>
>> ---
>>  arch/sh/include/asm/cpu_sh4.h           |    2 +
>>  arch/sh/include/asm/cpu_sh7757.h        |  263 +++++++++++++++
>>  board/renesas/sh7757lcr/Makefile        |   42 +++
>>  board/renesas/sh7757lcr/config.mk       |   28 ++
>>  board/renesas/sh7757lcr/lowlevel_init.S |  558 +++++++++++++++++++++++++++++++
>>  board/renesas/sh7757lcr/sh7757lcr.c     |  436 ++++++++++++++++++++++++
>>  board/renesas/sh7757lcr/spi-boot.c      |  111 ++++++
>>  board/renesas/sh7757lcr/u-boot.lds      |  101 ++++++
>>  boards.cfg                              |    1 +
>>  doc/README.sh7757lcr                    |   64 ++++
>>  include/configs/sh7757lcr.h             |  143 ++++++++
>>  11 files changed, 1749 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/sh/include/asm/cpu_sh7757.h
>>  create mode 100644 board/renesas/sh7757lcr/Makefile
>>  create mode 100644 board/renesas/sh7757lcr/config.mk
>>  create mode 100644 board/renesas/sh7757lcr/lowlevel_init.S
>>  create mode 100644 board/renesas/sh7757lcr/sh7757lcr.c
>>  create mode 100644 board/renesas/sh7757lcr/spi-boot.c
>>  create mode 100644 board/renesas/sh7757lcr/u-boot.lds
>>  create mode 100644 doc/README.sh7757lcr
>>  create mode 100644 include/configs/sh7757lcr.h
>
> Entry to MAINTAINERS missing.
>
> ...
>> +/* TMU0 */
>> +#define TSTR                 0xFE430004
>> +#define TOCR                 0xFE430000
>> +#define TSTR0                0xFE430004
>> +#define TCOR0                0xFE430008
>> +#define TCNT0                0xFE43000C
>> +#define TCR0                 0xFE430010
>> +#define TCOR1                0xFE430014
>> +#define TCNT1                0xFE430018
>> +#define TCR1                 0xFE43001C
>> +#define TCOR2                0xFE430020
>> +#define TCNT2                0xFE430024
>> +#define TCR2                 0xFE430028
>> +#define TCPR2                0xFE43002C
>
> Please use C structs to describe hardware registers.

Some IP of SH is different every CPU.
When we made structure to summarize these in, time suffers from a test
and thinks
that it is it for the cause of the bug.

I recommend a method using address it, and to read/write of register.

>
> ...
>> +/* DDR3IF */
>> +#define DDR3IF_BASE  0xfe800000
>> +#define DBSTATE0     (DDR3IF_BASE + 0x0008)
>> +#define DBSTATE1     (DDR3IF_BASE + 0x000c)
>> +#define DBACEN               (DDR3IF_BASE + 0x0010)
>> +#define DBRFEN               (DDR3IF_BASE + 0x0014)
>> +#define DBCMD                (DDR3IF_BASE + 0x0018)
>> +#define DBWAIT               (DDR3IF_BASE + 0x001c)
>> +#define DBKIND               (DDR3IF_BASE + 0x0020)
>> +#define DBCONF               (DDR3IF_BASE + 0x0024)
>> +#define DBTR0                (DDR3IF_BASE + 0x0040)
>> +#define DBTR1                (DDR3IF_BASE + 0x0044)
>> +#define DBTR2                (DDR3IF_BASE + 0x0048)
>> +#define DBTR3                (DDR3IF_BASE + 0x0050)
>> +#define DBTR4                (DDR3IF_BASE + 0x0054)
>> +#define DBTR5                (DDR3IF_BASE + 0x0058)
>> +#define DBTR6                (DDR3IF_BASE + 0x005c)
>> +#define DBTR7                (DDR3IF_BASE + 0x0060)
>> +#define DBTR8                (DDR3IF_BASE + 0x0064)
>> +#define DBTR9                (DDR3IF_BASE + 0x0068)
>> +#define DBTR10               (DDR3IF_BASE + 0x006c)
>> +#define DBTR11               (DDR3IF_BASE + 0x0070)
>> +#define DBTR12               (DDR3IF_BASE + 0x0074)
>> +#define DBTR13               (DDR3IF_BASE + 0x0078)
>> +#define DBTR14               (DDR3IF_BASE + 0x007c)
>> +#define DBTR15               (DDR3IF_BASE + 0x0080)
>> +#define DBTR16               (DDR3IF_BASE + 0x0084)
>> +#define DBTR17               (DDR3IF_BASE + 0x0088)
>> +#define DBTR18               (DDR3IF_BASE + 0x008c)
>> +#define DBTR19               (DDR3IF_BASE + 0x0090)
>> +#define DBADJ0               (DDR3IF_BASE + 0x00c0)
>> +#define DBADJ1               (DDR3IF_BASE + 0x00c4)
>> +#define DBADJ2               (DDR3IF_BASE + 0x00c8)
>> +#define DBADJ3               (DDR3IF_BASE + 0x00cc)
>> +#define DBRFCNF0     (DDR3IF_BASE + 0x00e0)
>> +#define DBRFCNF1     (DDR3IF_BASE + 0x00e4)
>> +#define DBRFCNF2     (DDR3IF_BASE + 0x00e8)
>> +#define DBCALCNF     (DDR3IF_BASE + 0x00f4)
>> +#define DBRNK0               (DDR3IF_BASE + 0x0100)
>> +#define DBPDCNT0     (DDR3IF_BASE + 0x0200)
>> +#define DBPDCNT1     (DDR3IF_BASE + 0x0204)
>> +#define DBPDCNT2     (DDR3IF_BASE + 0x0208)
>> +#define DBPDCNT3     (DDR3IF_BASE + 0x020c)
>> +#define DBPDLCK              (DDR3IF_BASE + 0x0280)
>> +#define DBPDRGA              (DDR3IF_BASE + 0x0290)
>> +#define DBPDRGD              (DDR3IF_BASE + 0x02a0)
>> +#define DBBS0CNT0    (DDR3IF_BASE + 0x0300)
>> +#define DBBS0CNT1    (DDR3IF_BASE + 0x0304)
>
> We don't allow base address + offset notation to access hardware
> registers. Please use C structs instead.

These macro was used in assembler.
It will be difficult to use these as a structure, I think.

Best regards,
  Nobuhiro

-- 
Nobuhiro Iwamatsu
   iwamatsu at {nigauri.org / debian.org}
   GPG ID: 40AD1FA6