[U-Boot] [PATCH 11/14] PHY: add some Vitesse phy support
Mingkai Hu
Mingkai.hu at freescale.com
Thu Jan 27 05:52:49 CET 2011
Port from tsec.c file to add support for vsc8221, vsc8211, vsc8601, vsc8641.
Signed-off-by: Mingkai Hu <Mingkai.hu at freescale.com>
---
drivers/net/fsl_phy.c | 119 +++++++++++++++++++++++++++++++++++++++++++++++++
drivers/net/fsl_phy.h | 21 +++++++++
2 files changed, 140 insertions(+), 0 deletions(-)
diff --git a/drivers/net/fsl_phy.c b/drivers/net/fsl_phy.c
index 1ba0ce1..a6ec614 100644
--- a/drivers/net/fsl_phy.c
+++ b/drivers/net/fsl_phy.c
@@ -242,6 +242,58 @@ static int genphy_shutdown(struct mii_info *phydev)
return 0;
}
+/* Vitesse VSC8211 */
+static int vsc8211_config(struct mii_info *mii_info)
+{
+ /* Override PHY config settings */
+ tsec_phy_write(mii_info, 0, MIIM_CIS8201_AUX_CONSTAT,
+ MIIM_CIS8201_AUXCONSTAT_INIT);
+ /* Set up the interface mode */
+ tsec_phy_write(mii_info, 0, MIIM_CIS8201_EXT_CON1,
+ MIIM_CIS8201_EXTCON1_INIT);
+ /* Configure some basic stuff */
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+
+ return 0;
+}
+
+static int vsc8211_parse_status(struct mii_info *mii_info)
+{
+ unsigned int speed;
+ unsigned int mii_reg;
+
+ mii_reg = tsec_phy_read(mii_info, 0, MIIM_CIS8201_AUX_CONSTAT);
+
+ if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
+ mii_info->duplex = DUPLEX_FULL;
+ else
+ mii_info->duplex = DUPLEX_HALF;
+
+ speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
+ switch (speed) {
+ case MIIM_CIS8201_AUXCONSTAT_GBIT:
+ mii_info->speed = SPEED_1000;
+ break;
+ case MIIM_CIS8201_AUXCONSTAT_100:
+ mii_info->speed = SPEED_100;
+ break;
+ default:
+ mii_info->speed = SPEED_10;
+ break;
+ }
+
+ return 0;
+}
+
+static int vsc8211_startup(struct mii_info *mii_info)
+{
+ /* Read the Status (2x to make sure link is right) */
+ genphy_update_link(mii_info);
+ vsc8211_parse_status(mii_info);
+
+ return 0;
+}
+
/* Vitesse VSC8244 */
static int vsc8244_parse_status(struct mii_info *mii_info)
{
@@ -280,6 +332,51 @@ static int vsc8244_startup(struct mii_info *mii_info)
return 0;
}
+/* Vitesse VSC8601 */
+int vsc8601_config(struct mii_info *mii_info)
+{
+ unsigned int reg;
+
+ /* Configure some basic stuff */
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+#ifdef CONFIG_SYS_VSC8601_SKEWFIX
+ tsec_phy_write(mii_info, 0, MIIM_VSC8601_EPHY_CON,
+ MIIM_VSC8601_EPHY_CON_INIT_SKEW);
+#if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
+ tsec_phy_write(mii_info, 0, PHY_EXT_PAGE_ACCESS, 1);
+#define VSC8101_SKEW \
+ (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12)
+ tsec_phy_write(mii_info, 0, MIIM_VSC8601_SKEW_CTRL, VSC8101_SKEW);
+ tsec_phy_write(mii_info, 0, PHY_EXT_PAGE_ACCESS, 0);
+#endif
+#endif
+ tsec_phy_write(mii_info, 0, MII_ADVERTISE, MII_ADVERTISE_INIT);
+
+ reg = tsec_phy_read(mii_info, 0, MII_BMCR);
+ reg |= BMCR_ANRESTART;
+ tsec_phy_write(mii_info, 0, MII_BMCR, reg);
+
+ return 0;
+}
+
+static struct phy_info phy_info_VSC8211 = {
+ "Vitesse VSC8211",
+ 0xfc4b0,
+ 0xffff0,
+ &vsc8211_config,
+ &vsc8211_startup,
+ &genphy_shutdown,
+};
+
+static struct phy_info phy_info_VSC8221 = {
+ "Vitesse VSC8221",
+ 0xfc550,
+ 0xffff0,
+ &genphy_config,
+ &vsc8244_startup,
+ &genphy_shutdown,
+};
+
static struct phy_info phy_info_VSC8244 = {
"Vitesse VSC8244",
0xfc6c0,
@@ -298,6 +395,24 @@ static struct phy_info phy_info_VSC8234 = {
&genphy_shutdown,
};
+static struct phy_info phy_info_VSC8601 = {
+ "Vitesse VSC8601",
+ 0x70420,
+ 0xffff0,
+ &vsc8601_config,
+ &vsc8244_startup,
+ &genphy_shutdown,
+};
+
+struct phy_info phy_info_VSC8641 = {
+ "Vitesse VSC8641",
+ 0x70430,
+ 0xffff0,
+ &genphy_config,
+ &vsc8244_startup,
+ &genphy_shutdown,
+};
+
static struct phy_info phy_info_generic = {
"Unknown/Generic PHY",
0x0,
@@ -308,8 +423,12 @@ static struct phy_info phy_info_generic = {
};
static struct phy_info *phy_info[] = {
+ &phy_info_VSC8211,
+ &phy_info_VSC8221,
&phy_info_VSC8244,
&phy_info_VSC8234,
+ &phy_info_VSC8601,
+ &phy_info_VSC8641,
&phy_info_generic
};
diff --git a/drivers/net/fsl_phy.h b/drivers/net/fsl_phy.h
index 8a8b6e8..d18cc58 100644
--- a/drivers/net/fsl_phy.h
+++ b/drivers/net/fsl_phy.h
@@ -34,7 +34,11 @@
#define PORT_MII 0x02
#define PORT_FIBRE 0x03
+/* PHY register offsets */
+#define PHY_EXT_PAGE_ACCESS 0x1f
+
#define MII_BMCR_INIT 0x00001140
+#define MII_ADVERTISE_INIT 0x1e1
/* MII Management Configuration Register */
#define MIIMCFG_RESET_MGMT 0x80000000
@@ -96,6 +100,18 @@
#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
+/* Cicada Auxiliary Control/Status Register */
+#define MIIM_CIS8201_AUX_CONSTAT 0x1c
+#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
+#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
+#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
+#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
+#define MIIM_CIS8201_AUXCONSTAT_100 0x0008
+
+/* Cicada Extended Control Register 1 */
+#define MIIM_CIS8201_EXT_CON1 0x17
+#define MIIM_CIS8201_EXTCON1_INIT 0x0000
+
/* Entry for Vitesse VSC8244 regs starts here */
/* Vitesse VSC8244 Auxiliary Control/Status Register */
#define MIIM_VSC8244_AUX_CONSTAT 0x1c
@@ -106,6 +122,11 @@
#define MIIM_VSC8244_AUXCONSTAT_100 0x0008
#define MIIM_CONTROL_INIT_LOOPBACK 0x4000
+/* Vitesse VSC8601 Extended PHY Control Register 1 */
+#define MIIM_VSC8601_EPHY_CON 0x17
+#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
+#define MIIM_VSC8601_SKEW_CTRL 0x1c
+
struct mii_info {
/* Information about the PHY type */
/* And management functions */
--
1.6.4
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