[U-Boot] [PATCH] ARM: MX5: Remove broken leftover TO-2 errata workaround
Stefano Babic
sbabic at denx.de
Thu Jul 14 10:16:51 CEST 2011
On 07/14/2011 09:13 AM, David Jander wrote:
> This check is broken. r3 does not contain the silicon revision.
>
> Signed-off-by: David Jander <david at protonic.nl>
> ---
Hi David,
> arch/arm/cpu/armv7/mx5/lowlevel_init.S | 5 -----
> 1 files changed, 0 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> index ee4150d..f17d200 100644
> --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> @@ -39,11 +39,6 @@
> orr r0, r0, #(1 << 23) /* disable write allocate combine */
> orr r0, r0, #(1 << 22) /* disable write allocate */
>
> - cmp r3, #0x10 /* r3 contains the silicon rev */
You are right. Nobody sets the r3 register, the test can be wrong.
> -
> - /* disable write combine for TO 2 and lower revs */
> - orrls r0, r0, #(1 << 25)
However, you also remove the setup for TO2. To fix the TO2 issue, we
should read correctly the revision number (from IIM or from a fixed
address, I do not remember now), and then apply the compare to the read
value.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
More information about the U-Boot
mailing list